US Patent Application 18365868. MEMORY MODULE WITH REDUCED ECC OVERHEAD AND MEMORY SYSTEM simplified abstract

MEMORY MODULE WITH REDUCED ECC OVERHEAD AND MEMORY SYSTEM

Organization Name

SAMSUNG ELECTRONICS CO., LTD.==Inventor(s)==

[[Category:Taekwoon Kim of Seoul (KR)]]

[[Category:Wonhyung Song of Osan-si (KR)]]

[[Category:Jangseok Choi of Seongnam-si (KR)]]

MEMORY MODULE WITH REDUCED ECC OVERHEAD AND MEMORY SYSTEM - A simplified explanation of the abstract

This abstract first appeared for US patent application 18365868 titled 'MEMORY MODULE WITH REDUCED ECC OVERHEAD AND MEMORY SYSTEM

Simplified Explanation

The patent application describes a memory system consisting of a memory module and a memory controller.

• The memory module contains data chips that store data and are divided into two sub-channels, each generating a different code word.
• These code words are used to fill a single cache line.
• The memory controller is responsible for managing the memory system.
• If a data chip fails, the memory controller detects it and copies the data from the failed chip to an ECC (Error Correction Code) chip.
• The memory controller then releases the mapping between the failed chip and the corresponding I/O (Input/Output) and establishes a new mapping between the ECC chip and the corresponding I/O pins.

Original Abstract Submitted

A memory system includes a memory module and a memory controller. The memory module includes data chips that store data and are assigned to a first sub-channel that generates a first code word or a second sub-channel that generates a second code word, where the first code word and the second code are used to fill a single cache line. The memory controller, upon detection of a hard-fail data chip among the data chips, copies data from the hard-fail data chip to the ECC chip, releases mapping between the hard-fail data chip and corresponding I/O, and defines new mapping between the ECC chip and the corresponding I/O pins.