US Patent Application 18061636. TEMPERATURE MARGIN SETTING METHOD FOR 3D INTEGRATED CIRCUIT simplified abstract

TEMPERATURE MARGIN SETTING METHOD FOR 3D INTEGRATED CIRCUIT

Organization Name

SAMSUNG ELECTRONICS CO., LTD.==Inventor(s)==

[[Category:Ki-Ok Kim of Suwon-si (KR)]]

[[Category:Jingon Lee of Suwon-si (KR)]]

[[Category:Mijeong Lim of Suwon-si (KR)]]

TEMPERATURE MARGIN SETTING METHOD FOR 3D INTEGRATED CIRCUIT - A simplified explanation of the abstract

This abstract first appeared for US patent application 18061636 titled 'TEMPERATURE MARGIN SETTING METHOD FOR 3D INTEGRATED CIRCUIT

Simplified Explanation

- The patent application describes a method for designing a 3D integrated circuit. - The method involves generating a distance-delay table based on a thermal analysis result. - The first timing path distance is calculated for the first chip in a 3D signal transfer path. - The second timing path distance is calculated for the second chip in the 3D signal transfer path. - The 3D timing path distance is calculated by summing the first and second timing path distances. - A temperature margin for the 3D timing path is set based on the distance-delay table and the 3D timing path distance.

Original Abstract Submitted

A method of designing a 3D integrated circuit includes generating a distance-delay table with respect to at least one of a first chip or a second chip stacked on the first chip, based on a thermal analysis result, calculating a first timing path distance with respect to a first timing path corresponding to the first chip in a 3D signal transfer path, calculating a second timing path distance with respect to a second timing path corresponding to the second chip in the 3D signal transfer path, calculating a 3D timing path distance by summing the first timing path distance and the second timing path distance, and setting a temperature margin with respect to a 3D timing path based on the distance-delay table and the 3D timing path distance.