Intel Corporation patent applications published on March 14th, 2024
Summary of the patent applications from Intel Corporation on March 14th, 2024
Intel Corporation has recently filed patents related to wireless medium access mechanisms, data transmission management, multi-camera dynamic calibration, and trusted execution environments.
Summary: - Wireless medium access mechanism for prioritized access by stations through reservation signals and high-priority contention policies. - Data transmission management method involving determining reference time points and time offsets for synchronized data transmission. - Multi-camera dynamic calibration technique for accurate calibration of multiple cameras in dynamic environments. - Trusted execution environment for secure communication and data processing between compute servers, accelerators, and service servers.
Notable Applications:
- Wireless communication systems
- Internet of Things (IoT) devices
- Industrial automation
- Audio and video streaming applications
- Real-time communication systems
- Computer vision, robotics, augmented reality, and surveillance systems
- Secure data processing in cloud computing
- Remote service requests with enhanced security.
Contents
- 1 Patent applications for Intel Corporation on March 14th, 2024
- 1.1 CHIPLET STATE AWARE AND DYNAMIC VOLTAGE REGULATOR EVENT HANDLING (17944310)
- 1.2 FREQUENCY OVERSHOOT AND VOLTAGE DROOP MITIGATION APPARATUS AND METHOD (18514807)
- 1.3 OFFSET SCALING IN LOAD/STORE MESSAGES (17944500)
- 1.4 DYNAMIC VOLTAGE AND FREQUENCY SCALING FOR MEMORY IN HETEROGENEOUS CORE ARCHITECTURES (17942415)
- 1.5 Regional Adjustment of Render Rate (18474361)
- 1.6 AUTOMATIC CODE GENERATION OF OPTIMIZED RTL VIA REDUNDANT CODE REMOVAL (18512518)
- 1.7 INSTRUCTION AND LOGIC FOR TRACKING FETCH PERFORMANCE BOTTLENECKS (18473088)
- 1.8 SCHEDULING OF THREADS FOR EXECUTION UTILIZING LOAD BALANCING OF THREAD GROUPS (18365595)
- 1.9 OFFLOAD COMPUTING PROTOCOL (18371881)
- 1.10 DISAGGREGATED COMPUTING FOR DISTRIBUTED CONFIDENTIAL COMPUTING ENVIRONMENT (18511296)
- 1.11 SELECTIVE CHECKING FOR ERRORS (17941960)
- 1.12 INSTRUCTION PREFETCH MECHANISM (18470553)
- 1.13 ADAPTIVE FABRIC ALLOCATION FOR LOCAL AND REMOTE EMERGING MEMORIES BASED PREDICTION SCHEMES (18371513)
- 1.14 TEMPERATURE AND VOLTAGE INSENSITIVE CROSSTALK CANCELLATION (17942516)
- 1.15 INSTRUCTION BASED CONTROL OF MEMORY ATTRIBUTES (18491474)
- 1.16 SYSTEMS AND METHODS FOR UPDATING MEMORY SIDE CACHES IN A MULTI-GPU CONFIGURATION (18516716)
- 1.17 NEURAL NETWORK SCHEDULING MECHANISM (18471843)
- 1.18 METHODS AND SYSTEMS FOR BUDGETED AND SIMPLIFIED TRAINING OF DEEP NEURAL NETWORKS (18371934)
- 1.19 MERGING ATOMICS TO THE SAME CACHE LINE (17944542)
- 1.20 TEMPORAL DATA STRUCTURES IN A RAY TRACING ARCHITECTURE (18372783)
- 1.21 COPPER CLAD LAMINATE (CCL) FOR PLATING PADS WITHIN A GLASS CAVITY FOR GLASS CORE APPLICATIONS (17943915)
- 1.22 FULL WAFER DEVICE WITH FRONT SIDE PASSIVE ELECTRONIC COMPONENTS (17930825)
- 1.23 FULL WAFER DEVICE WITH BACK SIDE INTERCONNECTS AND WAFER-SCALE INTEGRATION (17930841)
- 1.24 FULL WAFER DEVICE WITH BACK SIDE PASSIVE ELECTRONIC COMPONENTS (17930801)
- 1.25 SCALABLE HIGH SPEED HIGH BANDWIDTH IO SIGNALING PACKAGE ARCHITECTURE AND METHOD OF MAKING (18516579)
- 1.26 PATTERNABLE DIE ATTACH MATERIALS AND PROCESSES FOR PATTERNING (18513015)
- 1.27 INTEGRATED CIRCUIT SUPPORTS WITH MICROSTRIPS (18260810)
- 1.28 PATCH ACCOMMODATING EMBEDDED DIES HAVING DIFFERENT THICKNESSES (18511641)
- 1.29 DIODES WITH BACKSIDE CONTACT (17943812)
- 1.30 WIDE CHANNEL DIODE STRUCTURE INCLUDING SUB-FIN (17943819)
- 1.31 TRANSISTOR DEVICES WITH INTEGRATED DIODES (17943840)
- 1.32 TARGETED SUB-FIN ETCH DEPTH (17943815)
- 1.33 TRANSISTOR DEVICES WITH EXTENDED DRAIN (17943557)
- 1.34 NEIGHBORING GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DISJOINED EPITAXIAL SOURCE OR DRAIN REGIONS (18511604)
- 1.35 SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITHOUT FIN END GAP (18516595)
- 1.36 GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CHANNEL STRUCTURES USING SELECTIVE BOTTOM-UP APPROACH (18513028)
- 1.37 TECHNOLOGIES FOR GLASS CORE INDUCTOR (17943354)
- 1.38 BARRIER LAYER FOR DIELECTRIC RECESS MITIGATION (17940195)
- 1.39 GATE CUTS IN A GRATING PATTERN ACROSS AN INTEGRATED CIRCUIT (17943443)
- 1.40 GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DUAL NANORIBBON CHANNEL STRUCTURES (18510402)
- 1.41 GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING INSULATOR FIN ON INSULATOR SUBSTRATE (18514995)
- 1.42 EPITAXIAL REGIONS EXTENDING BETWEEN INNER GATE SPACERS (17940194)
- 1.43 FIN TRIM PLUG STRUCTURES WITH METAL FOR IMPARTING CHANNEL STRESS (17940944)
- 1.44 NANOWIRE TRANSISTOR STRUCTURE AND METHOD OF SHAPING (18514974)
- 1.45 CURRENT AND HEAT BALANCING CONSTANT VOLTAGE CHARGING (17942392)
- 1.46 TRANSISTOR OVER-VOLTAGE PROTECTION (17993412)
- 1.47 PRIVACY PRESERVING DIGITAL PERSONAL ASSISTANT (17931007)
- 1.48 SECURE MULTIPARTY COMPUTE USING HOMOMORPHIC ENCRYPTION (17931438)
- 1.49 MIGRATION FROM A LEGACY NETWORK APPLIANCE TO A NETWORK FUNCTION VIRTUALIZATION (NFV) APPLIANCE (18513261)
- 1.50 PACKET BUFFERING TECHNOLOGIES (18388780)
- 1.51 TECHNIQUES FOR A TRUSTED EXECUTION ENVIRONMENT AT A COMPUTE SERVER TO USE A REMOTE ACCELERATOR (17942466)
- 1.52 DETERMINING TRANSLATION SCALE IN A MULTI-CAMERA DYNAMIC CALIBRATION SYSTEM (18507593)
- 1.53 BLUETOOTH REPORT EVENTS FOR ULTRA LOW LATENCY (17940049)
- 1.54 APPARATUS, SYSTEM, AND METHOD OF WIRELESS MEDIUM PRIORITIZED ACCESS (18479008)
Patent applications for Intel Corporation on March 14th, 2024
CHIPLET STATE AWARE AND DYNAMIC VOLTAGE REGULATOR EVENT HANDLING (17944310)
Main Inventor
Jianwei Dai
FREQUENCY OVERSHOOT AND VOLTAGE DROOP MITIGATION APPARATUS AND METHOD (18514807)
Main Inventor
Praveen MOSALIKANTI
OFFSET SCALING IN LOAD/STORE MESSAGES (17944500)
Main Inventor
John Wiegert
DYNAMIC VOLTAGE AND FREQUENCY SCALING FOR MEMORY IN HETEROGENEOUS CORE ARCHITECTURES (17942415)
Main Inventor
Rizwana Begum
Regional Adjustment of Render Rate (18474361)
Main Inventor
Eric J. Asperheim
AUTOMATIC CODE GENERATION OF OPTIMIZED RTL VIA REDUNDANT CODE REMOVAL (18512518)
Main Inventor
Theo Drane
INSTRUCTION AND LOGIC FOR TRACKING FETCH PERFORMANCE BOTTLENECKS (18473088)
Main Inventor
Ahmad Yasin
SCHEDULING OF THREADS FOR EXECUTION UTILIZING LOAD BALANCING OF THREAD GROUPS (18365595)
Main Inventor
Balaji Vembu
OFFLOAD COMPUTING PROTOCOL (18371881)
Main Inventor
Fearghal O'Hare
DISAGGREGATED COMPUTING FOR DISTRIBUTED CONFIDENTIAL COMPUTING ENVIRONMENT (18511296)
Main Inventor
Reshma Lal
SELECTIVE CHECKING FOR ERRORS (17941960)
Main Inventor
Francesc Guim Bernat
INSTRUCTION PREFETCH MECHANISM (18470553)
Main Inventor
Vasileios Porpodas
ADAPTIVE FABRIC ALLOCATION FOR LOCAL AND REMOTE EMERGING MEMORIES BASED PREDICTION SCHEMES (18371513)
Main Inventor
Benjamin Graniello
TEMPERATURE AND VOLTAGE INSENSITIVE CROSSTALK CANCELLATION (17942516)
Main Inventor
Taner Sumesaglam
INSTRUCTION BASED CONTROL OF MEMORY ATTRIBUTES (18491474)
Main Inventor
Joydeep Ray
SYSTEMS AND METHODS FOR UPDATING MEMORY SIDE CACHES IN A MULTI-GPU CONFIGURATION (18516716)
Main Inventor
Altug Koker
NEURAL NETWORK SCHEDULING MECHANISM (18471843)
Main Inventor
Liwei Ma
METHODS AND SYSTEMS FOR BUDGETED AND SIMPLIFIED TRAINING OF DEEP NEURAL NETWORKS (18371934)
Main Inventor
Yiwen GUO
MERGING ATOMICS TO THE SAME CACHE LINE (17944542)
Main Inventor
Joydeep Ray
TEMPORAL DATA STRUCTURES IN A RAY TRACING ARCHITECTURE (18372783)
Main Inventor
Sven WOOP
COPPER CLAD LAMINATE (CCL) FOR PLATING PADS WITHIN A GLASS CAVITY FOR GLASS CORE APPLICATIONS (17943915)
Main Inventor
Brandon C. MARIN
FULL WAFER DEVICE WITH FRONT SIDE PASSIVE ELECTRONIC COMPONENTS (17930825)
Main Inventor
Abhishek A. Sharma
FULL WAFER DEVICE WITH BACK SIDE INTERCONNECTS AND WAFER-SCALE INTEGRATION (17930841)
Main Inventor
Abhishek A. Sharma
FULL WAFER DEVICE WITH BACK SIDE PASSIVE ELECTRONIC COMPONENTS (17930801)
Main Inventor
Abhishek A. Sharma
SCALABLE HIGH SPEED HIGH BANDWIDTH IO SIGNALING PACKAGE ARCHITECTURE AND METHOD OF MAKING (18516579)
Main Inventor
Sanka Ganesan
PATTERNABLE DIE ATTACH MATERIALS AND PROCESSES FOR PATTERNING (18513015)
Main Inventor
Bai NIE
INTEGRATED CIRCUIT SUPPORTS WITH MICROSTRIPS (18260810)
Main Inventor
Wenzhi Wang
PATCH ACCOMMODATING EMBEDDED DIES HAVING DIFFERENT THICKNESSES (18511641)
Main Inventor
Srinivas PIETAMBARAM
DIODES WITH BACKSIDE CONTACT (17943812)
Main Inventor
Nicholas A. Thomson
WIDE CHANNEL DIODE STRUCTURE INCLUDING SUB-FIN (17943819)
Main Inventor
Nicholas A. Thomson
TRANSISTOR DEVICES WITH INTEGRATED DIODES (17943840)
Main Inventor
Nicholas A. Thomson
TARGETED SUB-FIN ETCH DEPTH (17943815)
Main Inventor
Nicholas A. Thomson
TRANSISTOR DEVICES WITH EXTENDED DRAIN (17943557)
Main Inventor
Ayan Kar
NEIGHBORING GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DISJOINED EPITAXIAL SOURCE OR DRAIN REGIONS (18511604)
Main Inventor
Leonard P. GULER
SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITHOUT FIN END GAP (18516595)
Main Inventor
Szuya S. Liao
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CHANNEL STRUCTURES USING SELECTIVE BOTTOM-UP APPROACH (18513028)
Main Inventor
Nicole THOMAS
TECHNOLOGIES FOR GLASS CORE INDUCTOR (17943354)
Main Inventor
Brandon Christian Marin
BARRIER LAYER FOR DIELECTRIC RECESS MITIGATION (17940195)
Main Inventor
Tao Chu
GATE CUTS IN A GRATING PATTERN ACROSS AN INTEGRATED CIRCUIT (17943443)
Main Inventor
Shao-Ming Koh
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DUAL NANORIBBON CHANNEL STRUCTURES (18510402)
Main Inventor
Tanuj TRIVEDI
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING INSULATOR FIN ON INSULATOR SUBSTRATE (18514995)
Main Inventor
Aaron D. Lilak
EPITAXIAL REGIONS EXTENDING BETWEEN INNER GATE SPACERS (17940194)
Main Inventor
Tao Chu
FIN TRIM PLUG STRUCTURES WITH METAL FOR IMPARTING CHANNEL STRESS (17940944)
Main Inventor
Tao CHU
NANOWIRE TRANSISTOR STRUCTURE AND METHOD OF SHAPING (18514974)
Main Inventor
Erica J. THOMPSON
CURRENT AND HEAT BALANCING CONSTANT VOLTAGE CHARGING (17942392)
Main Inventor
Naoki Matsumura
TRANSISTOR OVER-VOLTAGE PROTECTION (17993412)
Main Inventor
Dharmaray Nedalgi
PRIVACY PRESERVING DIGITAL PERSONAL ASSISTANT (17931007)
Main Inventor
Jeremy Bottleson
SECURE MULTIPARTY COMPUTE USING HOMOMORPHIC ENCRYPTION (17931438)
Main Inventor
Kylan Race
MIGRATION FROM A LEGACY NETWORK APPLIANCE TO A NETWORK FUNCTION VIRTUALIZATION (NFV) APPLIANCE (18513261)
Main Inventor
Patrick CONNOR
PACKET BUFFERING TECHNOLOGIES (18388780)
Main Inventor
Md Ashiqur RAHMAN
TECHNIQUES FOR A TRUSTED EXECUTION ENVIRONMENT AT A COMPUTE SERVER TO USE A REMOTE ACCELERATOR (17942466)
Main Inventor
Utkarsh Y. KAKAIYA
DETERMINING TRANSLATION SCALE IN A MULTI-CAMERA DYNAMIC CALIBRATION SYSTEM (18507593)
Main Inventor
Avinash Kumar
BLUETOOTH REPORT EVENTS FOR ULTRA LOW LATENCY (17940049)
Main Inventor
Oren HAGGAI
APPARATUS, SYSTEM, AND METHOD OF WIRELESS MEDIUM PRIORITIZED ACCESS (18479008)
Main Inventor
Laurent Cariou
