17942415. DYNAMIC VOLTAGE AND FREQUENCY SCALING FOR MEMORY IN HETEROGENEOUS CORE ARCHITECTURES simplified abstract (Intel Corporation)
Contents
- 1 DYNAMIC VOLTAGE AND FREQUENCY SCALING FOR MEMORY IN HETEROGENEOUS CORE ARCHITECTURES
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 DYNAMIC VOLTAGE AND FREQUENCY SCALING FOR MEMORY IN HETEROGENEOUS CORE ARCHITECTURES - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Original Abstract Submitted
DYNAMIC VOLTAGE AND FREQUENCY SCALING FOR MEMORY IN HETEROGENEOUS CORE ARCHITECTURES
Organization Name
Inventor(s)
Rizwana Begum of Sachse TX (US)
Rohit Sharad Phatak of Hillsboro OR (US)
Eric Heit of Hillsboro OR (US)
Xiangdong Lou of Poway CA (US)
DYNAMIC VOLTAGE AND FREQUENCY SCALING FOR MEMORY IN HETEROGENEOUS CORE ARCHITECTURES - A simplified explanation of the abstract
This abstract first appeared for US patent application 17942415 titled 'DYNAMIC VOLTAGE AND FREQUENCY SCALING FOR MEMORY IN HETEROGENEOUS CORE ARCHITECTURES
Simplified Explanation
Embodiments described in the patent application focus on optimizing memory frequency based on the bandwidth and latency needs of different processing cores in a computer system. Adjustments to memory frequency are tailored to the type of core requesting more bandwidth or faster response, with energy-efficient cores receiving more conservative increases in frequency compared to high-performance cores. When memory traffic decreases, the frequency of memory is decreased more generously if the previous request for higher frequency came from an energy-efficient core rather than a high-performance core. By taking into account the type of core making the request, a balance between performance and power consumption can be achieved.
- Different processing cores in a computer system have varying bandwidth and latency needs.
- Memory frequency adjustments are customized based on the type of core requesting more bandwidth or faster response.
- Energy-efficient cores receive more conservative increases in memory frequency compared to high-performance cores.
- Memory frequency is decreased more generously when memory traffic decreases, especially if the previous request for higher frequency was from an energy-efficient core.
- Balancing performance and power consumption by considering the type of core making the request.
Potential Applications
This technology can be applied in various computing systems, such as servers, data centers, and high-performance computing environments, to optimize memory performance based on the specific requirements of different processing cores.
Problems Solved
This technology addresses the challenge of efficiently managing memory frequency to meet the diverse needs of heterogeneous processing cores, ensuring optimal performance while minimizing power consumption in a computer system.
Benefits
- Improved performance by optimizing memory frequency for different processing cores - Enhanced energy efficiency by adjusting memory frequency based on core type - Better balance between performance and power consumption in a computer system
Potential Commercial Applications
Optimizing memory frequency for heterogeneous processing cores can benefit industries such as cloud computing, artificial intelligence, and scientific research, where high-performance computing capabilities are essential for complex data processing tasks.
Unanswered Questions
How does this technology impact overall system reliability and stability?
This article does not delve into the potential effects of adjusting memory frequency on the reliability and stability of the computer system.
Are there any limitations or constraints in implementing this technology across different hardware configurations?
The patent application does not address any potential limitations or constraints that may arise when implementing this technology on various hardware configurations.
Original Abstract Submitted
Embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to optimizing memory frequency based on the bandwidth and latency needs of heterogeneous processing cores in a computer system. According to various embodiments, adjustments to the frequency of memory may be applied differently depending on the type of core requesting more bandwidth and/or faster response. According to various embodiments, the frequency is increased more sparingly for energy-efficient cores, while the frequency is increased more generously for high-performance cores. Additionally, when memory traffic decreases, the frequency of memory is decreased more generously when the previous request for higher frequency was from an energy-efficient core than a high-performance core. By considering the type of core that is requesting more bandwidth and/or faster response, performance and power consumption may be more optimally balanced.
