18511641. PATCH ACCOMMODATING EMBEDDED DIES HAVING DIFFERENT THICKNESSES simplified abstract (Intel Corporation)

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PATCH ACCOMMODATING EMBEDDED DIES HAVING DIFFERENT THICKNESSES

Organization Name

Intel Corporation

Inventor(s)

Srinivas Pietambaram of Gilbert AZ (US)

Robert Alan May of Chandler AZ (US)

Kristof Darmawikarta of Chandler AZ (US)

Hiroki Tanaka of Chandler AZ (US)

Rahul N. Manepalli of Chandler AZ (US)

Sri Ranga Sai Boyapati of Chandler AZ (US)

PATCH ACCOMMODATING EMBEDDED DIES HAVING DIFFERENT THICKNESSES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18511641 titled 'PATCH ACCOMMODATING EMBEDDED DIES HAVING DIFFERENT THICKNESSES

Simplified Explanation

The abstract describes a patent application for techniques to couple one or more surface dies to an interposer or motherboard, including a patch with multiple embedded dies of varying thickness.

  • The innovation involves a patch that can be used to connect surface dies to an interposer or motherboard.
  • The patch includes multiple embedded dies, each with a different thickness.
  • The microelectronic device formed using this patch can have improved connectivity and functionality.

Potential Applications

The technology could be applied in various industries such as:

  • Electronics manufacturing
  • Semiconductor production
  • Computer hardware development

Problems Solved

The innovation addresses the following issues:

  • Enhancing connectivity between surface dies and interposers/motherboards
  • Improving the overall performance and functionality of microelectronic devices

Benefits

The technology offers the following benefits:

  • Increased efficiency in microelectronic device manufacturing
  • Enhanced reliability and durability of electronic components
  • Potential for more compact and powerful devices

Potential Commercial Applications

  • "Innovative Patch Technology for Microelectronic Devices: Commercial Applications"

Unanswered Questions

How cost-effective is the implementation of this technology in mass production?

The article does not provide information on the cost implications of integrating this patch technology into large-scale manufacturing processes.

What are the potential limitations or drawbacks of using this patch in microelectronic devices?

The article does not discuss any potential downsides or challenges that may arise from utilizing this patch technology in practical applications.


Original Abstract Submitted

Techniques for a patch to couple one or more surface dies to an interposer or motherboard are provided. In an example, the patch can include multiple embedded dies. In an example, a microelectronic device can be formed to include a patch on an interposer, where the patch can include multiple embedded dies and each die can have a different thickness.