18516579. SCALABLE HIGH SPEED HIGH BANDWIDTH IO SIGNALING PACKAGE ARCHITECTURE AND METHOD OF MAKING simplified abstract (Intel Corporation)

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SCALABLE HIGH SPEED HIGH BANDWIDTH IO SIGNALING PACKAGE ARCHITECTURE AND METHOD OF MAKING

Organization Name

Intel Corporation

Inventor(s)

Sanka Ganesan of Chandler AZ (US)

Robert L. Sankman of Phoenix AZ (US)

Arghya Sain of Chandler AZ (US)

Sri Chaitra Jyotsna Chavali of Chandler AZ (US)

Lijiang Wang of Chandler AZ (US)

Cemil Geyik of Gilbert AZ (US)

SCALABLE HIGH SPEED HIGH BANDWIDTH IO SIGNALING PACKAGE ARCHITECTURE AND METHOD OF MAKING - A simplified explanation of the abstract

This abstract first appeared for US patent application 18516579 titled 'SCALABLE HIGH SPEED HIGH BANDWIDTH IO SIGNALING PACKAGE ARCHITECTURE AND METHOD OF MAKING

Simplified Explanation

The abstract describes an electronic package with a unique routing architecture, including multiple dies connected by a bridge and a routing patch with a different routing architecture.

  • The electronic package includes a package substrate with a first routing architecture.
  • It contains a first die and a second die on the package substrate.
  • The first die is connected to the second die by a bridge embedded in the package substrate.
  • There is a routing patch on the package substrate, electrically coupled to the second die.
  • The routing patch has a second routing architecture different from the first routing architecture.

Potential Applications

This technology could be applied in:

  • High-performance computing systems
  • Data centers
  • Telecommunications equipment

Problems Solved

This technology helps in:

  • Improving signal integrity
  • Reducing electromagnetic interference
  • Enhancing overall system performance

Benefits

The benefits of this technology include:

  • Increased data transfer speeds
  • Enhanced reliability
  • Compact design for space-saving

Potential Commercial Applications

  • "Innovative Routing Architecture for Electronic Packages in High-Performance Computing Systems"

Unanswered Questions

How does this technology impact power consumption in electronic packages?

This article does not address the specific impact of this technology on power consumption.

Are there any limitations to the size or complexity of electronic packages that can implement this routing architecture?

The article does not discuss any potential limitations regarding the size or complexity of electronic packages utilizing this routing architecture.


Original Abstract Submitted

Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, wherein the package substrate comprises a first routing architecture. In an embodiment, the electronic package further comprises a first die on the package substrate, a second die on the package substrate, wherein the first die is electrically coupled to the second die by a bridge embedded in the package substrate, and a routing patch on the package substrate. In an embodiment, the routing patch is electrically coupled to the second die, and wherein the routing patch comprises a second routing architecture that is different than the first routing architecture.

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