17943557. TRANSISTOR DEVICES WITH EXTENDED DRAIN simplified abstract (Intel Corporation)

TRANSISTOR DEVICES WITH EXTENDED DRAIN

Organization Name

Intel Corporation

Inventor(s)

Ayan Kar of Portland OR (US)

Nicholas A. Thomson of Hillsboro OR (US)

Kalyan C. Kolluru of Portland OR (US)

Benjamin Orr of Beaverton OR (US)

TRANSISTOR DEVICES WITH EXTENDED DRAIN - A simplified explanation of the abstract

This abstract first appeared for US patent application 17943557 titled 'TRANSISTOR DEVICES WITH EXTENDED DRAIN

Simplified Explanation

The integrated circuit structure described in the patent application includes a sub-fin, source and drain regions in contact with different portions of the sub-fin, a body made of semiconductor material above the sub-fin, and a gate structure on the body consisting of a gate electrode and a gate dielectric.

• The structure includes a sub-fin, source and drain regions, body, and gate structure.
• The gate structure has a gate electrode and a gate dielectric.
• The body extends laterally between the source and drain regions.
• The distance between the drain region and the gate electrode is at least two times the distance between the source region and the gate electrode.
• The body can be a nanoribbon, nanosheet, nanowire, or fin.

Potential Applications

This technology could be applied in:

• Advanced semiconductor devices
• High-performance integrated circuits
• Nanoelectronics

Problems Solved

This technology helps in:

• Improving performance and efficiency of integrated circuits
• Enhancing the functionality of semiconductor devices
• Enabling smaller and more powerful electronic devices

Benefits

The benefits of this technology include:

• Increased speed and efficiency of electronic devices
• Enhanced functionality and capabilities of integrated circuits
• Potential for smaller and more compact electronic devices

Potential Commercial Applications

Title: Applications of Integrated Circuit Structure with Sub-Fin and Gate Structure This technology could be commercially applied in:

• Semiconductor industry for manufacturing advanced chips
• Electronics industry for developing high-performance devices
• Research and development for creating innovative electronic products

Unanswered Questions

How does this technology impact power consumption in electronic devices?

This technology can potentially reduce power consumption in electronic devices by improving efficiency and performance, but the exact impact on power consumption needs further research and testing.

What are the scalability limitations of this integrated circuit structure?

While the technology shows promise for advanced semiconductor devices, the scalability limitations in terms of manufacturing processes and cost-effectiveness are not addressed in the patent application. Further studies are required to determine the scalability of this technology for mass production.

Original Abstract Submitted

An integrated circuit structure includes a sub-fin, a source region in contact with a first portion of the sub-fin, and a drain region in contact with a second portion of the sub-fin. A body including semiconductor material is above the sub-fin, where the body extends laterally between the source region and the drain region. A gate structure is on the body and includes (i) a gate electrode, and (ii) a gate dielectric between the gate electrode and the body. In an example, a first distance between the drain region and the gate electrode is at least two times a second distance between the source region and the gate electrode, where the first and second distances are measured in a same horizontal plane that runs in a direction parallel to the body. In an example, the body is a nanoribbon, a nanosheet, a nanowire, or a fin.