17943815. TARGETED SUB-FIN ETCH DEPTH simplified abstract (Intel Corporation)
Contents
- 1 TARGETED SUB-FIN ETCH DEPTH
TARGETED SUB-FIN ETCH DEPTH
Organization Name
Inventor(s)
Nicholas A. Thomson of Hillsboro OR (US)
Kalyan C. Kolluru of Portland OR (US)
Mauro J. Kobrinsky of Portland OR (US)
TARGETED SUB-FIN ETCH DEPTH - A simplified explanation of the abstract
This abstract first appeared for US patent application 17943815 titled 'TARGETED SUB-FIN ETCH DEPTH
Simplified Explanation
The patent application describes an integrated circuit structure with laterally adjacent first and second devices, each having diffusion regions, bodies with semiconductor material, and gate structures. The first device has a diffusion region with a lower section extending below the gate structure, while the second device has a similar configuration with a different height. Specifically, the first height is at least 2 nanometers greater than the second height.
- The integrated circuit structure includes laterally adjacent first and second devices.
- The first device has a diffusion region, a body with semiconductor material, and a gate structure.
- The second device also has a diffusion region, a body with semiconductor material, and a gate structure.
- The first diffusion region has a lower section that extends below the gate structure, with a specific height.
- The second diffusion region has a lower section that extends below the gate structure, with a different height.
- The first height is at least 2 nanometers greater than the second height.
Potential Applications
This technology could be applied in:
- Semiconductor manufacturing
- Integrated circuit design
- Electronics industry
Problems Solved
This technology helps in:
- Improving the performance of integrated circuits
- Enhancing the efficiency of semiconductor devices
Benefits
The benefits of this technology include:
- Better control over device characteristics
- Increased precision in semiconductor processing
- Enhanced overall circuit performance
Potential Commercial Applications
Optimizing Integrated Circuit Structures for Improved Performance
Unanswered Questions
How does this technology impact power consumption in integrated circuits?
The article does not delve into the specific effects on power consumption that this technology may have.
Are there any limitations to the scalability of this innovation in semiconductor manufacturing?
The article does not address any potential limitations or challenges related to the scalability of this technology.
Original Abstract Submitted
An integrated circuit structure includes laterally adjacent first and second devices. The first device has (i) a first diffusion region, (ii) a first body including semiconductor material extending laterally from the first diffusion region, and (iii) a first gate structure on the first body. The first diffusion region has a first lower section that extends below a lower surface of the first gate structure, the first lower section having a first height. The second device has (i) a second diffusion region, (ii) a second body including semiconductor material extending laterally from the second diffusion region, and (iii) a second gate structure on the second body. The second diffusion region has a second lower section that extends below a lower surface of the second gate structure, the second lower section having a second height. In an example, the first height is at least 2 nanometers greater than the second height.
