17940944. FIN TRIM PLUG STRUCTURES WITH METAL FOR IMPARTING CHANNEL STRESS simplified abstract (Intel Corporation)
Contents
- 1 FIN TRIM PLUG STRUCTURES WITH METAL FOR IMPARTING CHANNEL STRESS
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 FIN TRIM PLUG STRUCTURES WITH METAL FOR IMPARTING CHANNEL STRESS - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Unanswered Questions
- 1.10 Original Abstract Submitted
FIN TRIM PLUG STRUCTURES WITH METAL FOR IMPARTING CHANNEL STRESS
Organization Name
Inventor(s)
Feng Zhang of Hillsboro OR (US)
Minwoo Jang of Portland OR (US)
Yanbin Luo of Portland OR (US)
Chia-Ching Lin of Portland OR (US)
Ting-Hsiang Hung of Beaverton OR (US)
FIN TRIM PLUG STRUCTURES WITH METAL FOR IMPARTING CHANNEL STRESS - A simplified explanation of the abstract
This abstract first appeared for US patent application 17940944 titled 'FIN TRIM PLUG STRUCTURES WITH METAL FOR IMPARTING CHANNEL STRESS
Simplified Explanation
The patent application describes fin trim plug structures with metal for imparting channel stress in an integrated circuit structure.
- The integrated circuit structure includes a fin made of silicon with a top and sidewalls.
- A first isolation structure is located over one end of the fin.
- A gate structure with a gate electrode is positioned over the top and sidewalls of a region of the fin.
- A second isolation structure is located over the opposite end of the fin.
- Both isolation structures contain a dielectric material surrounding an isolated metal structure.
Potential Applications
This technology could be applied in the semiconductor industry for enhancing the performance of integrated circuits by introducing channel stress through the use of fin trim plug structures with metal.
Problems Solved
1. Enhancing the performance of integrated circuits by imparting channel stress. 2. Improving the efficiency of semiconductor devices through innovative structure design.
Benefits
1. Increased speed and efficiency of integrated circuits. 2. Enhanced reliability and performance of semiconductor devices. 3. Potential for miniaturization and improved power consumption.
Potential Commercial Applications
Optimizing Channel Stress in Integrated Circuits for Enhanced Performance
Unanswered Questions
How does this technology compare to existing methods of imparting channel stress in integrated circuits?
This article does not provide a direct comparison with traditional methods of introducing channel stress in integrated circuits.
What are the potential limitations or drawbacks of using fin trim plug structures with metal for imparting channel stress?
The article does not address any potential limitations or drawbacks associated with this technology.
Original Abstract Submitted
Fin trim plug structures with metal for imparting channel stress are described. In an example, an integrated circuit structure includes a fin including silicon, the fin having a top and sidewalls, wherein the top has a longest dimension along a direction. A first isolation structure is over a first end of the fin. A gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of a region of the fin. The gate structure is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end, the second isolation structure spaced apart from the gate structure along the direction. The first isolation structure and the second isolation structure both include a dielectric material laterally surrounding an isolated metal structure.
