17930841. FULL WAFER DEVICE WITH BACK SIDE INTERCONNECTS AND WAFER-SCALE INTEGRATION simplified abstract (Intel Corporation)

FULL WAFER DEVICE WITH BACK SIDE INTERCONNECTS AND WAFER-SCALE INTEGRATION

Organization Name

Intel Corporation

Inventor(s)

Abhishek A. Sharma of Hillsboro OR (US)

Tahir Ghani of Portland OR (US)

Wilfred Gomes of Portland OR (US)

Anand S. Murthy of Portland OR (US)

Sagar Suthram of Portland OR (US)

FULL WAFER DEVICE WITH BACK SIDE INTERCONNECTS AND WAFER-SCALE INTEGRATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 17930841 titled 'FULL WAFER DEVICE WITH BACK SIDE INTERCONNECTS AND WAFER-SCALE INTEGRATION

Simplified Explanation

The patent application describes full wafer devices with interconnect layers on the backside, including an active layer with active devices like transistors to control signal routing between different dies.

• The full wafer devices have interconnect layers on the backside.
• The backside interconnect layers connect different dies of the device.
• An active layer within the backside interconnect layers contains active devices such as transistors.
• The active devices can function as switches to manage signal routing between dies.

Potential Applications

The technology described in the patent application could be applied in:

• Integrated circuits
• Semiconductor devices
• Electronic systems

Problems Solved

This technology addresses issues such as:

• Efficient signal routing between different dies
• Enhanced connectivity in full wafer devices

Benefits

The benefits of this technology include:

• Improved performance in full wafer devices
• Enhanced functionality and flexibility in signal routing

Potential Commercial Applications

• "Innovative Backside Interconnect Layers for Full Wafer Devices" in Semiconductor Industry

Unanswered Questions

How does the active layer impact power consumption in the full wafer devices?

The patent application does not delve into the power consumption implications of the active layer.

Are there any limitations to the size or complexity of the full wafer devices that can incorporate this technology?

The patent application does not discuss any restrictions on the size or complexity of the full wafer devices utilizing this technology.

Original Abstract Submitted

Described herein are full wafer devices that include interconnect layers on a back side of the device. The backside interconnect layers couple together different dies of the full wafer device. The backside interconnect layers include an active layer that includes active devices, such as transistors. The active devices may act as switches, e.g., to control routing of signals between different dies of the full wafer device.