17941960. SELECTIVE CHECKING FOR ERRORS simplified abstract (Intel Corporation)
Contents
- 1 SELECTIVE CHECKING FOR ERRORS
SELECTIVE CHECKING FOR ERRORS
Organization Name
Inventor(s)
Francesc Guim Bernat of Barcelona (ES)
Karthik Kumar of Chandler AZ (US)
Amruta Misra of Bangalore (IN)
SELECTIVE CHECKING FOR ERRORS - A simplified explanation of the abstract
This abstract first appeared for US patent application 17941960 titled 'SELECTIVE CHECKING FOR ERRORS
Simplified Explanation
The patent application describes an apparatus that processes requests from a first device to monitor a memory address range of a second device for errors.
- The first circuitry processes requests specifying a memory address range of the second device to monitor for errors.
- The second circuitry compares data read from the second device with data read from memory to determine if an error has occurred.
Potential Applications
This technology could be applied in:
- Computer systems for error detection and correction.
- Data storage systems for ensuring data integrity.
Problems Solved
This technology helps in:
- Detecting errors in memory address ranges.
- Ensuring data accuracy and reliability.
Benefits
The benefits of this technology include:
- Improved system reliability.
- Enhanced data integrity.
- Efficient error detection and correction.
Potential Commercial Applications
- "Error Detection and Correction Technology for Enhanced Data Integrity" could be used in:
- Data centers.
- Cloud computing services.
Unanswered Questions
How does the apparatus handle multiple read requests targeting the same memory address range simultaneously?
The patent application does not specify how the apparatus manages concurrent read requests targeting the same memory address range.
What is the impact of the apparatus on system performance and latency?
The patent application does not discuss the potential effects of the apparatus on system performance and latency.
Original Abstract Submitted
An apparatus comprising first circuitry to process a request generated by a first device, the request specifying a memory address range of a second device to monitor for errors; and second circuitry to, based on a determination that a read request targets the memory address range of the second device, compare first data read from the second device with second data read from a memory to determine whether an error has occurred.
