18388780. PACKET BUFFERING TECHNOLOGIES simplified abstract (Intel Corporation)

PACKET BUFFERING TECHNOLOGIES

Organization Name

Intel Corporation

Inventor(s)

Md Ashiqur Rahman of Phoenix AZ (US)

Roberto Penaranda Cebrian of Santa Clara CA (US)

Anil Vasudevan of Portland OR (US)

Allister Alemania of North Plains OR (US)

Pedro Yebenes Segura of San Jose CA (US)

PACKET BUFFERING TECHNOLOGIES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18388780 titled 'PACKET BUFFERING TECHNOLOGIES

Simplified Explanation

The abstract describes a switch with circuitry that can select between different memory devices to store packets based on certain criteria.

• The switch circuitry selects between a first memory and multiple second memory devices to store incoming packets.
• Depending on the selection, the packet is stored in either the first memory or the chosen second memory device.
• The packet is associated with specific ports, and the selected second memory device is linked to a different port than the ones associated with the packet.

Potential Applications

This technology could be applied in networking equipment, data centers, and telecommunications systems to efficiently manage packet storage and routing.

Problems Solved

1. Efficient packet storage: By dynamically selecting memory devices based on specific criteria, the switch can optimize packet storage and retrieval. 2. Port association: The ability to link memory devices to specific ports helps in organizing and managing network traffic effectively.

Benefits

1. Improved performance: By intelligently selecting memory devices, the switch can enhance overall network performance and reduce latency. 2. Enhanced scalability: The flexibility in choosing memory devices allows for scalability and adaptability to varying network demands.

Potential Commercial Applications

Optimizing Packet Storage and Routing in Network Switches

Unanswered Questions

How does the switch determine the level of the first queue to make the selection between memory devices?

The abstract does not provide details on the specific criteria or algorithms used by the switch to determine the level of the first queue.

What are the specific technical specifications of the first memory and the multiple second memory devices?

The abstract does not mention the technical specifications or capabilities of the first memory or the multiple second memory devices used in the switch circuitry.

Original Abstract Submitted

Examples described herein relate to a switch. In some examples, the switch includes circuitry that is configured to: based on receipt of a packet and a level of a first queue, select among a first memory and a second memory device among multiple second memory devices to store the packet, based on selection of the first memory, store the packet in the first memory, and based on selection of the second memory device among multiple second memory devices, store the packet into the selected second memory device. In some examples, the packet is associated with an ingress port and an egress port, and the selected second memory device is associated with a third port that is different than the ingress port or the egress port associated with the packet.