Taiwan Semiconductor Manufacturing Company, Ltd. patent applications published on October 19th, 2023

Summary of the patent applications from Taiwan Semiconductor Manufacturing Company, Ltd. on October 19th, 2023

Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) has recently filed several patents related to semiconductor devices and memory technologies. These patents cover various aspects of memory arrays, memory devices, and circuit designs. Notable applications of these patents include the development of advanced memory technologies such as MRAM and FeRAM, as well as the design of hybrid fin devices and the use of carbon nanotubes in device fabrication.

Summary of recent patents filed by TSMC:

• Patent 1: Describes a semiconductor device with a memory array consisting of multiple layers, including a film stack, a memory layer, a selector layer, and word lines. The film stack is made up of alternating conductive and insulating layers.

• Patent 2: Describes an integrated chip with a memory device that includes a metal/dielectric layer between a bottom electrode and an upper electrode. The metal/dielectric layer is made up of a lower dielectric layer, an upper dielectric layer, and a metal layer separating them.

• Patent 3: Describes a type of MRAM device with a bottom electrode, a magnetic tunnel junction (MTJ) structure, and a top electrode. Spacers and an etch stop layer are added to the device structure.

• Patent 4: Describes a FeRAM device with a bottom electrode structure, a top electrode, and a ferroelectric structure in between. A dielectric sidewall spacer structure is placed on the ledge of the top electrode.

• Patent 5: Describes a three-dimensional memory device with stacking structures, isolation pillars, gate dielectric layers, channel layers, and conductive pillars.

• Patent 6: Describes a memory device with two transistors formed in different regions of a substrate, connected to source/drain structures and separated by an isolation structure.

• Patent 7: Describes a circuit with an input circuit, a level shifter circuit, an output circuit, and two feedback circuits. The circuit generates output signals based on input signals and enable signals.

• Patent 8: Describes a semiconductor package with a semiconductor die, an encapsulation layer, and at least one antenna structure embedded within the encapsulation layer.

• Patent 9: Describes a method for designing a hybrid fin device layout with single-fin and multi-fin active regions controlled by a wider gate.

• Patent 10: Describes a method for fabricating a device using carbon nanotubes, involving the deposition of a dielectric layer, growth of CNTs, creation of a dummy gate structure, addition of gate spacers, formation of source/drain epitaxy structures, replacement of the dummy gate structure with a metal gate structure, and creation of source/drain contacts.

Notable applications:

• Development of advanced memory technologies such as MRAM and FeRAM.
• Design of hybrid fin devices with different electrical characteristics.
• Use of carbon nanotubes in device fabrication.

Patent applications for Taiwan Semiconductor Manufacturing Company, Ltd. on October 19th, 2023

CONDUCTIVE PROBE, METHOD OF MANUFACTURING THE SAME, AND PROBE CARD DEVICE HAVING THE SAME (17804090)

Main Inventor

Chih-Chieh LIAO

ANTENNA TESTING DEVICE FOR HIGH FREQUENCY ANTENNAS (18339250)

Main Inventor

Chi-Chang LAI

SEMICONDUCTOR WAFER TESTING SYSTEM AND RELATED METHOD FOR IMPROVING EXTERNAL MAGNETIC FIELD WAFER TESTING (18337470)

Main Inventor

Harry-Hak-Lay Chuang

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE (17837827)

Main Inventor

Ching-Yu CHANG

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND APPARATUS FOR MANUFACTURING THE SEMICONDUCTOR DEVICE (18206970)

Main Inventor

Shinn-Sheng YU

COMPUTE-IN MEMORY (CIM) DEVICE AND COMPUTING METHOD THEREOF (17720935)

Main Inventor

Jui-Che TSAI

MEMORY CIRCUIT AND CACHE CIRCUIT CONFIGURATION (18341088)

Main Inventor

Hsien-Hsin Sean Lee

INTEGRATED CIRCUIT AND METHOD OF FORMING SAME AND A SYSTEM (18337245)

Main Inventor

Sheng-Hsiung CHEN

ELECTROMIGRATION EVALUATION METHODOLOGY WITH CONSIDERATION OF BOTH SELF-HEATING AND HEAT SINK THERMAL EFFECTS (18341400)

Main Inventor

Hsien Yu TSENG

METHOD FOR WRITING TO MAGNETIC RANDOM ACCESS MEMORY (18213176)

Main Inventor

Ji-Feng YING

Word Line Delay Interlock Circuit for Write Operation (18158489)

Main Inventor

Atul Katoch

WRITE ASSIST CIRCUIT FOR MEMORY DEVICE (17720154)

Main Inventor

Chia-Che CHUNG

NOVEL DYNAMIC INHIBIT VOLTAGE TO REDUCE WRITE POWER FOR RANDOM-ACCESS MEMORY (18336395)

Main Inventor

Zheng-Jun Lin

ION IMPLANTATION METHOD FOR REDUCING ROUGHNESS OF PATTERNED RESIST LINES (17659283)

Main Inventor

Chun-Liang Chen

CHIP PACKAGE STRUCTURE WITH NICKEL LAYER (18341052)

Main Inventor

Kuo-Ching HSU

MULTI-CHAMBER SEMICONDUCTOR PROCESSING SYSTEM WITH TRANSFER ROBOT TEMPERATURE ADJUSTMENT (17723372)

Main Inventor

Chia-Hsi Wang

MULTIPLE TRANSPORT CARRIER DOCKING DEVICE (18317312)

Main Inventor

Chih-Hung HUANG

LITHOGRAPHY METHOD TO REDUCE SPACING BETWEEN INTERCONNECT WIRES IN INTERCONNECT STRUCTURE (18339264)

Main Inventor

Yi-Nien Su

FIN FIELD-EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME (18337855)

Main Inventor

Yu-Chi Pan

COMPLEMENTARY MOS FETS VERTICALLY ARRANGED AND INCLUDING MULTIPLE DIELECTRIC LAYERS SURROUNDING THE MOS FETS (18213758)

Main Inventor

Mark VAN DAL

SEMICONDUCTOR PACKAGE WITH STIFFENER STRUCTURE AND METHOD FORMING THE SAME (18336960)

Main Inventor

Wensen Hung

MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE (18342745)

Main Inventor

Chih-Chia Hu

SEMICONDUCTOR STRUCTURE WITH CONDUCTIVE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME (17721557)

Main Inventor

Jia-Heng WANG

HYBRID INTERCONNECT STRUCTURE FOR SELF ALIGNED VIA (18340079)

Main Inventor

Shin-Yi Yang

SEMICONDUCTOR DEVICE INCLUDING GRAPHENE INTERCONNECT AND METHOD OF MAKING THE SEMICONDUCTOR DEVICE (17720988)

Main Inventor

Shu-Wei LI

INTERCONNECTION STRUCTURE AND METHODS OF FORMING THE SAME (17722386)

Main Inventor

Pei-Yu CHOU

DIFFUSION BARRIER LAYER FOR CONDUCTIVE VIA TO DECREASE CONTACT RESISTANCE (18342889)

Main Inventor

Hsiu-Wen Hsueh

THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURES AND METHODS OF FORMING THE SAME (18341788)

Main Inventor

Chung-Yu Lu

CHIP PACKAGE AND METHOD OF FORMING THE SAME (18337044)

Main Inventor

Yu-Hsiang Hu

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF (18213759)

Main Inventor

Tsung-Chieh HSIAO

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF (17719390)

Main Inventor

Jen-Jui Yu

PACKAGE STRUCTURE WITH WARPAGE-CONTROL ELEMENT (18336516)

Main Inventor

Hao-Jan PEI

Semiconductor Packages and Methods of Forming the Same (18336592)

Main Inventor

Chen-Hua Yu

PACKAGE STRUCTURE WITH DUMMY DIE (18336435)

Main Inventor

Hsien-Wei CHEN

MASK TRANSFER METHOD (AND RELATED APPARATUS) FOR A BUMPING PROCESS (18332069)

Main Inventor

Ching-Sheng Chu

METHOD OF MANUFACTURING CONDUCTORS FOR SEMICONDUCTOR DEVICE (18341369)

Main Inventor

Kam-Tou SIO

IMAGE SENSOR PIXEL AND METAL SHIELDING OF CHARGE STORAGE DEVICE OF IMAGE SENSOR PIXEL FORMED BY ONE STEP PROCESS (18213320)

Main Inventor

Cheng-Yen Li

EXTRA DOPED REGION FOR BACK-SIDE DEEP TRENCH ISOLATION (18336100)

Main Inventor

Chun-Yuan Chen

DEVICE STRUCTURE AND METHODS OF FORMING THE SAME (18211561)

Main Inventor

Tsung-Chieh HSIAO

SEMICONDUCTOR DEVICE WITH AIR GAP ON GATE STRUCTURE AND METHOD FOR FORMING THE SAME (18334605)

Main Inventor

Tien-Lu LIN

METHOD AND STRUCTURE FOR GATE-ALL-AROUND DEVICES (17723685)

Main Inventor

Chun-Fai Cheng

SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME (18212258)

Main Inventor

Lin-Yu HUANG

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME (17721668)

Main Inventor

Ming-Lung CHENG

METHOD FOR FORMING EPITAXIAL SOURCE/DRAIN FEATURES AND SEMICONDUCTOR DEVICES FABRICATED THEREOF (18211055)

Main Inventor

Jung-Hung Chang

SEMICONDUCTOR STRUCTURE (18341100)

Main Inventor

Wei-Hao LIAO

SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME (17722381)

Main Inventor

YU-LIEN HUANG

FINFET AND GATE-ALL-AROUND FET WITH SELECTIVE HIGH-K OXIDE DEPOSITION (18337767)

Main Inventor

Tsung-Han TSAI

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME (18337039)

Main Inventor

Jui-Fen Chien

Semiconductor Devices And Methods Of Fabricating The Same (17719614)

Main Inventor

Chun-Fai Cheng

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME (17724434)

Main Inventor

Mahaveer Sathaiya DHANYAKUMAR

Gates of Hybrid-Fin Devices (17815898)

Main Inventor

Yi-Juei Lee

SEMICONDUCTOR PACKAGE WITH ANTENNA AND METHOD OF FORMING THE SAME (18337019)

Main Inventor

Wen-Shiang Liao

LEVEL SHIFTER CIRCUIT AND METHOD OF OPERATING THE SAME (18333284)

Main Inventor

Yu-Lun OU

Brief explanation

The abstract describes a circuit that consists of several components, including an input circuit, a level shifter circuit, an output circuit, and two feedback circuits. The input circuit is connected to a voltage supply and is designed to receive a first input signal and generate a second input signal. The level shifter circuit is connected to a different voltage supply and generates a first and second signal based on either the enable signal or the first input signal. The output circuit is connected to the level shifter circuit and the second voltage supply, and it generates an output signal and two feedback signals in response to the first signal. The two feedback circuits receive the enable signal, the inverted enable signal, and the corresponding first and second feedback signals.

Abstract

A circuit includes an input circuit, a level shifter circuit, an output circuit, and a first and a second feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second input signal. The level shifter circuit is coupled to a second voltage supply, and configured to generate at least a first and second signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the second voltage supply, and configured to generate at least an output signal, a first and second feedback signal responsive to the first signal. The first and second feedback circuit are configured to receive the enable signal, and the inverted enable signal, and the corresponding first and second feedback signal.

MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF (18338673)

Main Inventor

Jhon-Jhy Liaw

Brief explanation

This abstract describes a memory device that consists of two transistors formed in different regions of a substrate. The first transistor has a structure that sticks out from the substrate and is connected to a source/drain structure. The second transistor has multiple semiconductor layers stacked vertically, with source/drain structures connected to the ends of these layers. The first and second transistors are separated from each other by an isolation structure.

Abstract

A memory device includes a first transistor formed in a first region of a substrate. The first transistor includes a structure protruding from the substrate, and a first source/drain (S/D) structure coupled to a first end of the protruding structure. The memory device includes a second transistor formed in a second region of the substrate. The second transistor includes a number of first semiconductor layers that are vertically spaced apart from one another, a second S/D structure coupled to a first end of the first semiconductor layers; and a third S/D structure coupled to a second end of the first semiconductor layers. The first region and the second region are laterally separated from each other by an isolation structure.

THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF (18338344)

Main Inventor

Meng-Han Lin

Brief explanation

The abstract describes a three-dimensional memory device and its manufacturing method. The device consists of two stacking structures made of alternating insulating and conductive layers. Isolation pillars are placed between the stacking structures, extending laterally and protruding into the stacking structures. This creates cell regions between the stacking structures. Gate dielectric layers are formed in the cell regions, covering the sidewalls of the stacking structures and isolation pillars. Channel layers are then added, covering the inner surface of the gate dielectric layers. Finally, conductive pillars are placed within the cell regions, surrounded by the channel layers.

Abstract

A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes first and second stacking structures, isolation pillars, gate dielectric layers, channel layers and conductive pillars. The stacking structures are laterally spaced apart from each other. The stacking structures respectively comprises alternately stacked insulating layers and conductive layers. The isolation pillars laterally extend between the stacking structures. The isolation pillars further protrude into the stacking structures, and a space between the stacking structures is divided into cell regions. The gate dielectric layers are respectively formed in one of the cell regions, and cover opposing sidewalls of the stacking structures and sidewalls of the isolation pillars. The channel layers respectively cover an inner surface of one of the gate dielectric layers. The conductive pillars are separately located within the cell regions, and are laterally surrounded by the channel layers.

METHOD AND STRUCTURES PERTAINING TO IMPROVED FERROELECTRIC RANDOM-ACCESS MEMORY (FeRAM) (18336093)

Main Inventor

Tzu-Yu Chen

Brief explanation

The abstract describes a type of memory device called a ferroelectric random access memory (FeRAM). This FeRAM device has a bottom electrode structure and a top electrode, with a ferroelectric structure in between. The top electrode is narrower than the ferroelectric structure, creating a ledge. A dielectric sidewall spacer structure is placed on this ledge and covers the outer sides of the top electrode.

Abstract

Some embodiments relate to a ferroelectric random access memory (FeRAM) device. The FeRAM device includes a bottom electrode structure and a top electrode overlying the ferroelectric structure. The top electrode has a first width as measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure has a second width as measured between outermost sidewalls of the ferroelectric structure. The second width is greater than the first width such that the ferroelectric structure includes a ledge that reflects a difference between the first width and the second width. A dielectric sidewall spacer structure is disposed on the ledge and covers the outermost sidewalls of the top electrode.

MAGNETO-RESISTIVE RANDOM-ACCESS MEMORY (MRAM) DEVICES WITH SELF-ALIGNED TOP ELECTRODE VIA (18336790)

Main Inventor

Wei-Hao LIAO

Brief explanation

The abstract describes a type of MRAM (Magnetic Random Access Memory) device. It consists of several layers including a bottom electrode, a magnetic tunnel junction (MTJ) structure, and a top electrode. Spacers are placed on the sides of the top electrode and the MTJ structure. An etch stop layer is added on top of the spacers, covering their surfaces. Finally, a top electrode via is created on the top electrode and the etch stop layer.

Abstract

An MRAM device includes a bottom electrode over a substrate, a magnetic tunnel junction (MTJ) structure on the bottom electrode and a top electrode on the MTJ structure. The MRAM device also includes spacers on sidewalls of the top electrode and the MTJ structure. The MRAM device further includes a first etch stop layer on the spacers. A bottommost surface of the first etch stop layer covers a topmost surface of the spacers. In addition, the MRAM device includes a top electrode via on the top electrode and the first etch stop layer.

INTERCALATED METAL/DIELECTRIC STRUCTURE FOR NONVOLATILE MEMORY DEVICES (18336088)

Main Inventor

Mauricio Manfrini

Brief explanation

The abstract describes an integrated chip that includes a memory device. The memory device has a structure consisting of a bottom electrode, an upper electrode, and a metal/dielectric layer in between. The metal/dielectric layer is made up of a lower dielectric layer, an upper dielectric layer, and a metal layer separating them. This structure is placed on top of a semiconductor substrate.

Abstract

Some embodiments relate to an integrated chip including a memory device. The memory device includes a bottom electrode disposed over a semiconductor substrate. An upper electrode is disposed over the bottom electrode. An intercalated metal/dielectric structure is sandwiched between the bottom electrode and the upper electrode. The intercalated metal/dielectric structure comprises a lower dielectric layer over the bottom electrode, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer.

MEMORY CELL, SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL, AND MANUFACTURING METHOD THEREOF (18342723)

Main Inventor

Kai-Tai Chang

Brief explanation

This abstract describes a semiconductor device that includes a memory array. The memory array consists of multiple layers, including a film stack, a memory layer, a selector layer, and word lines. The film stack is made up of alternating conductive and insulating layers. Each conductive layer is composed of two materials in direct contact with each other, with the second material having a lower resistivity than the first material.

Abstract

A semiconductor device includes a substrate and a memory array disposed over the substrate. The memory array includes at least one film stack disposed over the substrate, a memory layer disposed over the substrate and covering a sidewall and a top of the film stack, a selector layer disposed on the memory layer, and at least one word line disposed on the selector layer and extending transversely with respect to the film stack. The film stack includes conductive layers and insulating layers alternately arranged, each conductive layer includes a first material and a second material in direct contact with each other, and a resistivity value of the second material is lower than a resistivity value of the first material.