US Patent Application 18342745. MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE simplified abstract
Contents
MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Hsien-Wei Chen of Hsinchu City (TW)
Ming-Fa Chen of Taichung City (TW)
Sen-Bor Jan of Tainan City (TW)
MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE - A simplified explanation of the abstract
- This abstract for appeared for US patent application number 18342745 Titled 'MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE'
Simplified Explanation
The abstract describes a method for manufacturing a semiconductor structure. The process involves several steps, including forming a conductive via that extends from a lower portion of a first interconnect structure into a first semiconductor substrate. An upper portion of the first interconnect structure is then formed on top of the conductive via. A first surface dielectric layer is applied on top of the upper portion, and a first and second bonding connectors are formed within the dielectric layer. The first bonding connector makes contact with an upper-level interconnecting layer of the first interconnect structure, while the second bonding connector, which is narrower than the first, makes contact with a lower-level interconnecting layer. The top surface of the conductive via is positioned between the upper-level interconnecting layer and the first semiconductor substrate.
Original Abstract Submitted
A manufacturing method of a semiconductor structure includes at least the following steps. Forming a first tier includes forming a conductive via extending from a lower portion of a first interconnect structure into a first semiconductor substrate underlying the lower portion; forming an upper portion of the first interconnect structure on the conductive via and the lower portion; forming a first surface dielectric layer on the upper portion; and forming a first and a second bonding connectors in the first surface dielectric layer. The first bonding connector extends to be in contact with an upper-level interconnecting layer of the first interconnect structure, the second bonding connector is narrower than the first bonding connector and extends to be in contact with a lower-level interconnecting layer of the first interconnect structure, and a top surface of the conductive via is between the upper-level interconnecting layer and the first semiconductor substrate.
