US Patent Application 18338344. THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract
Contents
THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Chun-Fu Cheng of Hsinchu County (TW)
Feng-Cheng Yang of Hsinchu County (TW)
Sheng-Chen Wang of Hsinchu City (TW)
Han-Jong Chia of Hsinchu City (TW)
THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A simplified explanation of the abstract
- This abstract for appeared for US patent application number 18338344 Titled 'THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF'
Simplified Explanation
The abstract describes a three-dimensional memory device and its manufacturing method. The device consists of two stacking structures made of alternating insulating and conductive layers. Isolation pillars are placed between the stacking structures, extending laterally and protruding into the stacking structures. This creates cell regions between the stacking structures. Gate dielectric layers are formed in the cell regions, covering the sidewalls of the stacking structures and isolation pillars. Channel layers are then added, covering the inner surface of the gate dielectric layers. Finally, conductive pillars are placed within the cell regions, surrounded by the channel layers.
Original Abstract Submitted
A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes first and second stacking structures, isolation pillars, gate dielectric layers, channel layers and conductive pillars. The stacking structures are laterally spaced apart from each other. The stacking structures respectively comprises alternately stacked insulating layers and conductive layers. The isolation pillars laterally extend between the stacking structures. The isolation pillars further protrude into the stacking structures, and a space between the stacking structures is divided into cell regions. The gate dielectric layers are respectively formed in one of the cell regions, and cover opposing sidewalls of the stacking structures and sidewalls of the isolation pillars. The channel layers respectively cover an inner surface of one of the gate dielectric layers. The conductive pillars are separately located within the cell regions, and are laterally surrounded by the channel layers.
