US Patent Application 17815898. Gates of Hybrid-Fin Devices simplified abstract

Gates of Hybrid-Fin Devices

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Yi-Juei Lee of Hsinchu City (TW)

Cheng-Tang Li of Hsinchu City (TW)

Huang-Chao Chang of Hsinchu City (TW)

Bi-Fen Wu of Taichung City (TW)

Gates of Hybrid-Fin Devices - A simplified explanation of the abstract

• This abstract for appeared for US patent application number 17815898 Titled 'Gates of Hybrid-Fin Devices'

Simplified Explanation

The abstract describes a method for designing a hybrid fin device layout. This device has two regions: a single-fin active region and a multi-fin active region. The gate, which controls the flow of electrical current, is positioned over both regions. The gate is wider in one direction than the other. The single-fin region and a portion of the gate create a fin-based device with one electrical characteristic, while the multi-fin region and another portion of the gate create a fin-based device with a different electrical characteristic. The method involves adjusting the width of the gate to minimize the difference between the two electrical characteristics.

Original Abstract Submitted

An exemplary method includes receiving a hybrid fin device layout for a hybrid fin device that includes a gate disposed over a single-fin active region and a multi-fin active region. The single-fin active region and the multi-fin active region extend lengthwise along a first direction. The gate extends lengthwise along a second direction, the second direction is different than the first direction, and the gate has a width along the first direction. The single-fin active region and a first portion of the gate form a first fin-based device having a first electrical characteristic. The multi-fin active region and a second portion of the gate form a second fin-based device having a second electrical characteristic that is different than the first electrical characteristic. The method further includes tuning the width of the gate to reduce a difference between the first electrical characteristic and the second electrical characteristic.