US Patent Application 18158489. Word Line Delay Interlock Circuit for Write Operation simplified abstract
Contents
Word Line Delay Interlock Circuit for Write Operation
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Sergiy Romanovskyy of Ottawa (CA)
Word Line Delay Interlock Circuit for Write Operation - A simplified explanation of the abstract
- This abstract for appeared for US patent application number 18158489 Titled 'Word Line Delay Interlock Circuit for Write Operation'
Simplified Explanation
The abstract describes a word line interlock circuit that is used in electronic devices. The circuit includes a first logic gate, an interlock circuit, and a delay circuit. The first logic gate receives a reset signal and the interlock circuit is connected to the output of the first logic gate. The interlock circuit generates a first signal and controls the operation of the first logic gate. The delay circuit is connected to the output of the interlock circuit and receives the first signal. It delays the first signal to generate a clock pulse width signal, which is then fed back to the interlock circuit. The interlock circuit selectively operates the first logic gate in order to prevent any changes in the reset signal from being transmitted to the delay circuit.
Original Abstract Submitted
Systems, methods, and devices are described herein for a word line interlock circuit. A device includes a first logic gate, an interlock circuit, and a delay circuit. The first logic gate is configured to receive a reset signal. The interlock circuit is coupled to an output of the first logic gate and is configured to generate a first signal and selectively operate the first logic gate. The delay circuit is coupled to an output of the interlock circuit and is configured to receive the first signal from the interlock circuit and delay the first signal to generate a clock pulse width signal that is fed back to the interlock circuit. In response to the reset signal changing logic states, the selective operation of the first logic gate prevents changing edges of the reset signal from being transmitted to the delay circuit.
