US Patent Application 18213758. COMPLEMENTARY MOS FETS VERTICALLY ARRANGED AND INCLUDING MULTIPLE DIELECTRIC LAYERS SURROUNDING THE MOS FETS simplified abstract
COMPLEMENTARY MOS FETS VERTICALLY ARRANGED AND INCLUDING MULTIPLE DIELECTRIC LAYERS SURROUNDING THE MOS FETS
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Gerben Doornbos of Kessel-Lo (BE)
COMPLEMENTARY MOS FETS VERTICALLY ARRANGED AND INCLUDING MULTIPLE DIELECTRIC LAYERS SURROUNDING THE MOS FETS - A simplified explanation of the abstract
- This abstract for appeared for US patent application number 18213758 Titled 'COMPLEMENTARY MOS FETS VERTICALLY ARRANGED AND INCLUDING MULTIPLE DIELECTRIC LAYERS SURROUNDING THE MOS FETS'
Simplified Explanation
The abstract describes a method for forming a fin structure in a semiconductor device. The fin structure includes multiple layers, including sacrificial layers and semiconductor layers. A dummy gate is formed over the semiconductor layers, and a sidewall spacer layer is formed on the sides of the dummy gate. The dummy gate is then removed, creating a space for the gate. The first insulating layer is etched in the gate space, exposing the semiconductor layers and sacrificial layers. The sacrificial layers are then removed, and a gate dielectric layer and gate electrode layer are formed.
Original Abstract Submitted
A fin including a bottom portion, a first sacrificial layer disposed over the bottom portion, a first semiconductor layer disposed over the first sacrificial layer, a second sacrificial layer disposed over the first semiconductor layer and a second semiconductor layer disposed over the second sacrificial layer, is formed. The second semiconductor layer protrudes from a first insulating layer. A dummy gate is formed over the second semiconductor layer. A sidewall spacer layer is formed on side faces of the dummy gate. A first dielectric layer is formed over the dummy gate and the sidewall spacer layer. The dummy gate is removed, thereby forming a gate space. The first insulating layer is etched in the gate space, thereby exposing the first semiconductor layer and the first and second sacrificial layers. The first and second sacrificial layers are removed. A gate dielectric layer and a gate electrode layer are formed.
