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| − | '''Summary of the patent applications from Micron Technology, Inc. on November 9th, 2023'''
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| − | Micron Technology, Inc. has recently filed several patents related to integrated circuits, memory systems, and microelectronic devices. These patents cover various aspects of memory arrays, memory cells, memory systems, transistors, and electronic systems. The organization's innovative technologies aim to improve memory performance, power efficiency, and error check functionality.
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| − | Summary:
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| − | Micron Technology, Inc. has filed patents for:
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| − | - Integrated circuits with memory arrays consisting of strings of memory cells made up of laterally-spaced memory blocks.
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| − | - Apparatuses with multiple memory cells arranged in a memory cell array region, along with word lines and insulating walls in the peripheral region.
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| − | - Memory systems that include memory components and a controller, which stores data items in separate memory regions based on their contexts.
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| − | - Keeper devices used in hybrid loop unrolled DFE circuits, which selectively output signals from equalizers based on the previous bit value to save power.
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| − | - Structures called inter-gate dielectric structures, placed between adjacent gates in transistors, memory devices, and systems.
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| − | - Microelectronic devices with vertical inverters, pillar structures, and vertical transistors connected to conductive lines.
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| − | - Methods, systems, and devices for self-repair verification in memory systems, involving replacing memory cells and comparing data to determine successful repair.
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| − | - Error check functionality in memory devices that store encoded data, where intentional errors are introduced and an indicator is determined based on read results.
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| − | - Methods for programming memory cells in blocks, involving precharging and applying programming voltages to selected cells.
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| − | - Processing devices in memory systems that connect data blocks using wordline connections driven by a single string driver.
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| − | Notable Applications:
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| − | * Integrated circuits with memory arrays consisting of strings of memory cells made up of laterally-spaced memory blocks.
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| − | * Memory systems that store data items in separate memory regions based on their contexts.
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| − | * Microelectronic devices with vertical inverters, pillar structures, and vertical transistors connected to conductive lines.
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| − | * Methods for self-repair verification in memory systems, involving replacing memory cells and comparing data to determine successful repair.
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| − | * Error check functionality in memory devices that store encoded data, where intentional errors are introduced and an indicator is determined based on read results.
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| − | * Methods for programming memory cells in blocks, involving precharging and applying programming voltages to selected cells.
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| − | * Processing devices in memory systems that connect data blocks using wordline connections driven by a single string driver.
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| | ==Patent applications for Micron Technology, Inc. on November 9th, 2023== | | ==Patent applications for Micron Technology, Inc. on November 9th, 2023== |
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| | Zhenming Zhou | | Zhenming Zhou |
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| − | '''Brief explanation'''
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| − | The present disclosure describes a system component, such as a memory sub-system controller, that can adaptively manage memory based on component reliabilities.
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| − | * The system component accesses configuration data to determine the reliability grade of different groups of memory components.
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| − | * Based on the reliability grade of each group, the system component selects appropriate media management operations.
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| − | * This adaptive media management helps optimize memory usage and performance.
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| − | * The system component can dynamically adjust its operations based on the reliability of the memory components.
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| − | * This technology improves the overall reliability and efficiency of memory systems.
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| − |
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| − | '''Abstract'''
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| − | Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to provide adaptive media management based on memory component reliabilities. The controller can access configuration data to determine a reliability grade associated with individual groups of the memory components. The controller can then adaptively select between different media management operations based on the reliability grade associated with each individual group of the memory components.
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| | ===FREQUENCY REGULATION FOR MEMORY MANAGEMENT COMMANDS ([[US Patent Application 17662187. FREQUENCY REGULATION FOR MEMORY MANAGEMENT COMMANDS simplified abstract|17662187]])=== | | ===FREQUENCY REGULATION FOR MEMORY MANAGEMENT COMMANDS ([[US Patent Application 17662187. FREQUENCY REGULATION FOR MEMORY MANAGEMENT COMMANDS simplified abstract|17662187]])=== |
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| | Bryan David Kerstetter | | Bryan David Kerstetter |
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| − | '''Brief explanation'''
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| − | The patent application describes methods, systems, and devices for frequency regulation in memory management commands.
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| − | * Memory devices have counters for each monitoring area, which are incremented for each activate command received.
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| − | * If the first counter reaches a threshold, an activate command to that area is ignored.
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| − | * If the second counter fails to reach a threshold, a memory management command to that area is ignored.
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| − | * The memory device maintains the value of the second counter and decrements the first counter in this case.
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| − | * If the second counter reaches the threshold, the memory device performs a memory management operation and decrements both counters.
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| − |
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| − | '''Abstract'''
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| − | Methods, systems, and devices for frequency regulation for memory management commands are described. A memory device may maintain a respective first counter and second counter for each monitoring area of the memory device, where the counters may be incremented for each activate command received for the corresponding monitoring area. If the first counter satisfies a first threshold, an activate command issued to the monitoring area may be ignored. If the second counter fails to satisfy a second threshold, a memory management command issued to the monitoring area may be ignored and the memory device may maintain a value of the second counter, while decrementing the first counter. Alternatively, if the second counter satisfies the second threshold, the memory device may perform a memory management operation associated with a received memory management command and may decrement the first counter and the second counter.
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| | ===MEMORY MANAGEMENT PROCEDURES FOR WRITE BOOST MODE ([[US Patent Application 17630113. MEMORY MANAGEMENT PROCEDURES FOR WRITE BOOST MODE simplified abstract|17630113]])=== | | ===MEMORY MANAGEMENT PROCEDURES FOR WRITE BOOST MODE ([[US Patent Application 17630113. MEMORY MANAGEMENT PROCEDURES FOR WRITE BOOST MODE simplified abstract|17630113]])=== |
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| | Xing Wang | | Xing Wang |
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| − |
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| − | '''Brief explanation'''
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| − | The patent application describes methods, systems, and devices for memory management procedures in a memory system's write boost mode.
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| − | * The memory system receives a command to write data.
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| − | * The data is initially written to a first location in the memory system using a first mode that stores one bit per memory cell.
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| − | * Based on certain parameters meeting specific thresholds, a first portion of the data is selected to be rewritten using a second mode that stores two or more bits per memory cell.
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| − | * The selected first portion of the data is then written to a second location in the memory system using the second mode.
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| − | * The remaining second portion of the data is maintained at the original first location in the memory system.
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| − |
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| − | '''Abstract'''
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| − | Methods, systems, and devices for memory management procedures for write boost mode are described. A memory system may receive a command to write data. The memory system may write the data to a first location of the memory system using a first mode for storing one bit per memory cell based on receiving the command. The memory system may select a first portion of the data to rewrite to the memory system using a second mode for storing two or more bits per memory cell based on one or more parameters satisfying one or more thresholds. The memory system may write the first portion of the data to a second location of the memory system using the second mode based on selecting the first portion of the data. The memory system may maintain a second portion of the data at the first location of the memory system.
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| | ===REUSING OR REPURPOSING MICROELECTRONIC DEVICES, AND ASSOCIATED METHODS, DEVICES, AND SYSTEMS ([[US Patent Application 17661973. REUSING OR REPURPOSING MICROELECTRONIC DEVICES, AND ASSOCIATED METHODS, DEVICES, AND SYSTEMS simplified abstract|17661973]])=== | | ===REUSING OR REPURPOSING MICROELECTRONIC DEVICES, AND ASSOCIATED METHODS, DEVICES, AND SYSTEMS ([[US Patent Application 17661973. REUSING OR REPURPOSING MICROELECTRONIC DEVICES, AND ASSOCIATED METHODS, DEVICES, AND SYSTEMS simplified abstract|17661973]])=== |
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| | Srinivasa Anuradha Bulusu | | Srinivasa Anuradha Bulusu |
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| − | '''Brief explanation'''
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| − | The patent application describes methods for reusing and repurposing microelectronic devices.
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| − | * The method involves receiving information about a specific secondary application for a microelectronic device.
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| − | * Health information about the microelectronic device is accessed.
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| − | * The health information is used to determine if the microelectronic device is suitable for the selected secondary application.
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| − | * The patent also covers associated devices and systems related to this method.
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| − | '''Abstract'''
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| − | Methods of reusing and/or repurposing microelectronic devices are disclosed. A method may include receiving an indication of a selected secondary application for a microelectronic device and accessing health information for the microelectronic device. The method may further include determining whether the microelectronic device is fit for the selected secondary application responsive to the health information. Associated devices and systems are also disclosed.
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| | ===DISTRIBUTED POWER UP FOR A MEMORY SYSTEM ([[US Patent Application 17737539. DISTRIBUTED POWER UP FOR A MEMORY SYSTEM simplified abstract|17737539]])=== | | ===DISTRIBUTED POWER UP FOR A MEMORY SYSTEM ([[US Patent Application 17737539. DISTRIBUTED POWER UP FOR A MEMORY SYSTEM simplified abstract|17737539]])=== |
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| | Giuseppe Cariello | | Giuseppe Cariello |
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| − | '''Brief explanation'''
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| − | The patent application describes methods, systems, and devices for distributed power up in a memory system.
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| − | * The memory system receives a command from a host system to initialize a set of memory devices.
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| − | * The memory system selects a first memory device from the set and reads a first operational parameter from a second memory device in a separate controller.
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| − | * The memory system then reads a set of second operational parameters from the first memory device, where each parameter corresponds to a respective memory device in the set.
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| − | * The innovation aims to improve the power-up process of memory systems by distributing the initialization process across multiple devices.
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| − | * This approach allows for efficient and optimized power-up of memory devices, enhancing overall system performance.
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| − | * By reading operational parameters from separate devices, the memory system can ensure proper initialization and configuration of each memory device.
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| − | * The invention can be applied to various memory systems, such as solid-state drives (SSDs) or computer memory modules.
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| − |
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| − | '''Abstract'''
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| − | Methods, systems, and devices for distributed power up for a memory system are described. The method may include a memory system receiving, from a host system, a command to initialize a set of memory devices included in a memory system. Upon receiving the command, the memory system may select a first memory device from the set of memory devices and read, from a second memory device in a controller separate from the set of memory devices, a first operational parameter corresponding to the first memory device. The memory system may then read, from the first memory device, a set of second operational parameters, each second operational parameter of the set of second operational parameters corresponding to a respective memory device of the set of memory devices.
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| | ===MULTI-PARTITION FILE SYSTEM FOR STORING VIDEO STREAMS IN A MANAGED NON-VOLATILE MEMORY DEVICE ([[US Patent Application 17842197. MULTI-PARTITION FILE SYSTEM FOR STORING VIDEO STREAMS IN A MANAGED NON-VOLATILE MEMORY DEVICE simplified abstract|17842197]])=== | | ===MULTI-PARTITION FILE SYSTEM FOR STORING VIDEO STREAMS IN A MANAGED NON-VOLATILE MEMORY DEVICE ([[US Patent Application 17842197. MULTI-PARTITION FILE SYSTEM FOR STORING VIDEO STREAMS IN A MANAGED NON-VOLATILE MEMORY DEVICE simplified abstract|17842197]])=== |
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| | Lei PAN | | Lei PAN |
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| − | '''Brief explanation'''
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| − | The patent application describes technologies for storing streaming data efficiently. Here are the key points:
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| − | * The system determines if the size of the streaming data meets a certain threshold and if it is sequential data.
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| − | * If the size and sequential nature of the data meet the criteria, it is written to the first partition of a file system.
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| − | * If the size of the data does not meet the threshold or if it is a specific type of metadata, it is written to the second partition of the file system.
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| − | * The file system has multiple partitions to organize and store the streaming data effectively.
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| − |
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| − | '''Abstract'''
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| − | Technologies for storing streaming data include, in some embodiments, in response to determining that the chunk size satisfies a chunk size threshold and the streaming data is sequential data of a size that satisfies a threshold sequential data size, writing the sequential data to a first file system partition of a file system comprising a plurality of file system partitions, and in response to determining that the chunk size does not satisfy the chunk size threshold or the chunk size satisfies the chunk size threshold and the streaming data is the first type of metadata, writing the streaming data to a second file system partition of the plurality of file system partitions.
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| | ===MEMORY READ CALIBRATION BASED ON MEMORY DEVICE-ORIGINATED METADATA CHARACTERIZING VOLTAGE DISTRIBUTIONS ([[US Patent Application 17735458. MEMORY READ CALIBRATION BASED ON MEMORY DEVICE-ORIGINATED METADATA CHARACTERIZING VOLTAGE DISTRIBUTIONS simplified abstract|17735458]])=== | | ===MEMORY READ CALIBRATION BASED ON MEMORY DEVICE-ORIGINATED METADATA CHARACTERIZING VOLTAGE DISTRIBUTIONS ([[US Patent Application 17735458. MEMORY READ CALIBRATION BASED ON MEMORY DEVICE-ORIGINATED METADATA CHARACTERIZING VOLTAGE DISTRIBUTIONS simplified abstract|17735458]])=== |
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| | Dung Viet Nguyen | | Dung Viet Nguyen |
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| − | '''Brief explanation'''
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| − | The patent application describes systems and methods for memory read calibration based on metadata provided by memory devices.
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| − | * Memory devices have a memory array with multiple memory cells connected to wordlines and bitlines.
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| − | * The controller of the memory device receives metadata values that characterize the voltage distributions of a subset of memory cells connected to bitlines.
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| − | * These metadata values reflect the conductive state of the bitlines, indicating the threshold voltage distributions of the memory cells.
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| − | * Based on the received metadata values, the controller determines a read voltage adjustment value.
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| − | * This read voltage adjustment value is then applied when reading the subset of memory cells, improving the accuracy and reliability of the read operation.
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| − |
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| − | '''Abstract'''
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| − | Described are systems and methods for memory read calibration based on memory device-originated metadata characterizing voltage distributions. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines; and a controller coupled to the memory array, the controller to perform operations comprising: receiving one or more metadata values characterizing threshold voltage distributions of a subset of the plurality of memory cells connected to one or more bitlines, wherein the one or more metadata values reflect a conductive state of the one or more bitlines; determining a read voltage adjustment value based on the one or more metadata values; and applying the read voltage adjustment value for reading the subset of the plurality of memory cells.
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| | ===CONFIGURABLE BUFFERED I/O FOR MEMORY SYSTEMS ([[US Patent Application 17735583. CONFIGURABLE BUFFERED I/O FOR MEMORY SYSTEMS simplified abstract|17735583]])=== | | ===CONFIGURABLE BUFFERED I/O FOR MEMORY SYSTEMS ([[US Patent Application 17735583. CONFIGURABLE BUFFERED I/O FOR MEMORY SYSTEMS simplified abstract|17735583]])=== |
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| | Jose Rey C. De Luna | | Jose Rey C. De Luna |
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| − | '''Brief explanation'''
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| − | - The present disclosure describes a system component that can be configured as a buffer device.
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| − | - This buffer device is placed between a processing device and a set of memory components.
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| − | - The buffer device can be configured to connect a certain number of front-side channels to a certain number of back-side channels.
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| − | - The configuration data for the buffer device can come from an external source or be stored in a configuration register during manufacturing.
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| − | - The configuration data can also be determined based on control pins of the buffer device.
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| − | - Overall, this innovation allows for flexible configuration of the buffer device to optimize the connection between the processing device and memory components.
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| − |
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| − | '''Abstract'''
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| − | Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to provide a configurable buffer device. The configuration buffer device is coupled between a processing device and a set of memory components. The configurable buffer device can be configured based on configuration data to couple a first quantity of front-side channels to a second quantity of back-side channels. The configuration data can be received from an external source, such as the processing device, or can be stored in a configuration register at manufacture. The configuration data can also be generated or determined based on one or more pins of the buffer device that control how many font-side channels and how many back-side channels to enable/disable.
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| | ===ENABLING MULTIPLE DATA CAPACITY MODES AT A MEMORY SUB-SYSTEM ([[US Patent Application 18349849. ENABLING MULTIPLE DATA CAPACITY MODES AT A MEMORY SUB-SYSTEM simplified abstract|18349849]])=== | | ===ENABLING MULTIPLE DATA CAPACITY MODES AT A MEMORY SUB-SYSTEM ([[US Patent Application 18349849. ENABLING MULTIPLE DATA CAPACITY MODES AT A MEMORY SUB-SYSTEM simplified abstract|18349849]])=== |
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| | Fangfang Zhu | | Fangfang Zhu |
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| − | '''Brief explanation'''
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| − | The patent application describes a method for determining whether a memory sub-system operates at full capacity or reduced capacity.
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| − | * The full capacity mode allows access to data through a set of memory devices using a number of physical data channels that matches the number of logical data channels.
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| − | * The reduced capacity mode allows access to data through a fewer number of physical data channels compared to the logical data channels.
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| − | * A data structure is updated to include mappings between physical and logical data channels based on the determination of the memory sub-system mode.
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| − | * The updated data structure is used to execute memory access operations for accessing data items in memory cells of the memory devices.
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| − |
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| − | '''Abstract'''
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| − | A determination is made of whether a memory sub-system operates in a full capacity mode or a reduced capacity mode. The full capacity mode corresponds to accessing data residing at a set of memory devices via a number of physical data channels that corresponds to a number of logical data channels. The reduced capacity mode corresponds to accessing the data via a number of physical data channels that is less than the number of logical data channels. A data structure is updated to include one or more mappings between physical data channels and logical data channels according to the determination. A memory access operation to access a data item at memory cells of at least one of the set of memory devices is executed based on the one or more mappings of the data structure.
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| | ===BOOT PROCESSES FOR STORAGE SYSTEMS ([[US Patent Application 17661983. BOOT PROCESSES FOR STORAGE SYSTEMS simplified abstract|17661983]])=== | | ===BOOT PROCESSES FOR STORAGE SYSTEMS ([[US Patent Application 17661983. BOOT PROCESSES FOR STORAGE SYSTEMS simplified abstract|17661983]])=== |
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| | Sourin SARKAR | | Sourin SARKAR |
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| − | '''Brief explanation'''
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| − | - The patent application describes a method for implementing a fast bootup process for memory devices in a storage system.
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| − | - The fast bootup process excludes the measurement of information retrieved from a memory device during the bootup process.
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| − | - The controller of the storage system receives a command to enable the fast bootup process.
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| − | - The controller enables the fast bootup process and disables the normal bootup process, which includes the measurement of information from the memory device.
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| − | - The purpose of this innovation is to speed up the bootup process for storage systems by skipping the measurement step.
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| − | '''Abstract'''
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| − | Implementations described herein relate to boot processes for memory devices. In some implementations, a controller of a storage system receives a command for enabling a fast bootup process for the storage system. The fast bootup process may exclude a measurement of information retrieved from a memory device of the storage system during the fast bootup process. The controller may enable the fast bootup process based on the command. The controller may disable a normal bootup process for the storage system based on the fast bootup process being enabled. The normal bootup process may include a measurement of information retrieved from the memory device during the normal bootup process.
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| | ===CUSTOM ERROR RECOVERY IN SELECTED REGIONS OF A DATA STORAGE DEVICE ([[US Patent Application 18352613. CUSTOM ERROR RECOVERY IN SELECTED REGIONS OF A DATA STORAGE DEVICE simplified abstract|18352613]])=== | | ===CUSTOM ERROR RECOVERY IN SELECTED REGIONS OF A DATA STORAGE DEVICE ([[US Patent Application 18352613. CUSTOM ERROR RECOVERY IN SELECTED REGIONS OF A DATA STORAGE DEVICE simplified abstract|18352613]])=== |
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| | Alex Frolikov | | Alex Frolikov |
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| − | '''Brief explanation'''
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| − | The patent application describes a memory sub-system with non-volatile media that can allocate multiple namespaces.
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| − | * Namespaces are identified by a command from a host system and have error recovery parameters associated with them.
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| − | * The controller of the memory sub-system configures the namespace on the non-volatile media based on the error recovery parameters provided.
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| − | * The error recovery parameters are stored in association with the namespace.
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| − | * The controller also controls error recovery operations for data access within the namespace according to the stored error recovery parameters.
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| − | '''Abstract'''
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| − | A memory sub-system having non-volatile media on which multiple namespaces are allocated. A command from a host system has an identification of a namespace and at least one error recovery parameter. A controller of the memory sub-system configures the namespace on the non-volatile media according to the at least one error recovery parameter, stores the at least one error recovery parameter in association with the namespace, and controls error recovery operations for data access in the namespace in accordance with the at least one error recovery parameter stored in association with the namespace.
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| | ===PERFORMANCE BENCHMARK FOR HOST PERFORMANCE BOOSTER ([[US Patent Application 17597985. PERFORMANCE BENCHMARK FOR HOST PERFORMANCE BOOSTER simplified abstract|17597985]])=== | | ===PERFORMANCE BENCHMARK FOR HOST PERFORMANCE BOOSTER ([[US Patent Application 17597985. PERFORMANCE BENCHMARK FOR HOST PERFORMANCE BOOSTER simplified abstract|17597985]])=== |
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| | Bin Zhao | | Bin Zhao |
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| − |
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| − | '''Brief explanation'''
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| − | The patent application describes methods, systems, and devices for a performance benchmark for a host performance booster.
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| − |
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| − | * The memory system receives read commands from a host system.
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| − | * The memory system detects a pattern of random physical addresses in the read commands.
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| − | * Based on the detected pattern, the memory system increases the space in its cache.
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| − | * The increased space may be used for mapping between logical block addresses and physical addresses.
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| − | * The memory system determines whether the rate of cache hits for a portion of the mapping satisfies a threshold.
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| − | * Based on this determination, the memory system decides whether to activate a host performance booster mode.
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| − |
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| − | '''Abstract'''
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| − | Methods, systems, and devices for performance benchmark for host performance booster are described. The memory system may receive a plurality of read commands from a host system. The memory system may detect a pattern of random physical addresses as part of the plurality of read commands and increase an amount of space in a cache of the memory system based on the detected pattern. In some cases, the amount of space may be used for mapping between logical block addresses and physical addresses. The memory system may determine, for a different plurality of read commands, whether a rate of cache hits for a portion of the mapping satisfies a threshold. In some cases, the memory system may determine whether to activate a host performance booster mode based on determining whether the rate of cache hits satisfies the threshold.
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| | ===TECHNIQUES FOR A FRAGMENT CURSOR ([[US Patent Application 17633523. TECHNIQUES FOR A FRAGMENT CURSOR simplified abstract|17633523]])=== | | ===TECHNIQUES FOR A FRAGMENT CURSOR ([[US Patent Application 17633523. TECHNIQUES FOR A FRAGMENT CURSOR simplified abstract|17633523]])=== |
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| | Xu Zhang | | Xu Zhang |
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| − | '''Brief explanation'''
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| − | The patent application describes methods, systems, and devices for a fragment cursor.
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| − | * A memory system receives write commands for data fragments and stores them in a cache.
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| − | * The cursor in the cache is designed to store data fragments smaller than a certain size threshold.
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| − | * When a memory management operation occurs, such as power down or data relocation, the cached data fragments are written to a block of memory cells using the cursor.
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| − | * The cursor may have a different associated mapping unit compared to other cursors in the memory system.
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| − |
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| − | '''Abstract'''
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| − | Methods, systems, and devices for techniques for a fragment cursor are described. A memory system may receive one or more write commands, each write command corresponding to a data fragment. The memory device may store the data fragments to a cursor (e.g., a fragment cursor) in a cache upon receiving the write commands, the cursor configured to store data fragments with a size less than a fragment size threshold (e.g., a page). The memory system may detect a memory management operation (e.g., power down, cache synchronization, data relocation, etc.) and write the cached data fragments to a block of memory cells of a memory device using the cursor. In some examples, the cursor may have a different associated mapping unit than other cursors of the memory system.
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| | ===MEMORY WRITE PERFORMANCE TECHNIQUES ([[US Patent Application 17633525. MEMORY WRITE PERFORMANCE TECHNIQUES simplified abstract|17633525]])=== | | ===MEMORY WRITE PERFORMANCE TECHNIQUES ([[US Patent Application 17633525. MEMORY WRITE PERFORMANCE TECHNIQUES simplified abstract|17633525]])=== |
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| | Bin Zhao | | Bin Zhao |
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| − |
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| − | '''Brief explanation'''
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| − | The patent application describes methods, systems, and devices for improving memory write performance.
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| − | * A memory system receives a sequence of commands from a host system.
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| − | * The memory system analyzes the logical block addresses of the commands to determine their relationship.
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| − | * Based on this relationship, the memory system may delay performing certain memory management operations for a duration.
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| − | * Memory management operations can include garbage collection, power operations, cache synchronization, data relocation, etc.
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| − | * The memory system determines if the quantity of write commands with non-consecutive logical block addresses exceeds a threshold.
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| − | * If the threshold is exceeded, the memory system may perform some commands during the duration.
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| − | * At the end of the duration, the memory system performs the memory management operation.
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| − |
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| − | '''Abstract'''
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| − | Methods, systems, and devices for memory write performance techniques are described. A memory system may receive a sequence of commands, for example from a host system. Based on a relationship between logical block addresses of the sequence of commands, the memory system may delay performing a memory management operation (e.g., a garbage collection procedure, a power operation, a cache synchronization operation, a data relocation operation, or the like) for a duration. For example, the memory system may determine whether a quantity of write commands in the sequence that include non-consecutive logical block addresses exceeds a threshold. In some cases, the memory system may perform one or more commands in the sequence during the duration. Subsequently (e.g., at the end of the duration), the memory system may perform the memory management operation.
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| | | | |
| | ===VALIDITY MAPPING TECHNIQUES ([[US Patent Application 17630453. VALIDITY MAPPING TECHNIQUES simplified abstract|17630453]])=== | | ===VALIDITY MAPPING TECHNIQUES ([[US Patent Application 17630453. VALIDITY MAPPING TECHNIQUES simplified abstract|17630453]])=== |
| Line 305: |
Line 120: |
| | Xing Wang | | Xing Wang |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes methods, systems, and devices for validity mapping techniques in a memory device.
| |
| − |
| |
| − | * The memory device uses a change log to update a mapping that indicates whether data stored at respective physical addresses is valid.
| |
| − | * When the memory device receives a command associated with data having a set of addresses, it sets an entry in the change log based on whether the addresses are consecutive.
| |
| − | * The memory device identifies whether the set of addresses are consecutive and sets a flag in the change log entry to indicate this.
| |
| − | * The memory device then updates one or more entries of the mapping corresponding to the change log entry to indicate whether the addresses store valid data.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Methods, systems, and devices for validity mapping techniques are described. A memory device may use a change log to update a mapping that indicates whether data stored at respective physical addresses is valid. For example, the memory device may receive a command associated with data having a corresponding set of addresses (whether logical block addresses or physical addresses). The memory device may set an entry of the change log based on whether the set of addresses are consecutive. For example, the memory device may identify whether the set of addresses are consecutive and may set a flag in the entry of the change log to indicate whether the addresses are consecutive. Then, the memory device may update one or more entries of the mapping corresponding to the entry of the change log to indicate whether the addresses corresponding to the one or more entries of the mapping store valid data.
| |
| | | | |
| | ===STORING A LOGICAL-TO-PHYSICAL MAPPING IN NAND MEMORY ([[US Patent Application 18223843. STORING A LOGICAL-TO-PHYSICAL MAPPING IN NAND MEMORY simplified abstract|18223843]])=== | | ===STORING A LOGICAL-TO-PHYSICAL MAPPING IN NAND MEMORY ([[US Patent Application 18223843. STORING A LOGICAL-TO-PHYSICAL MAPPING IN NAND MEMORY simplified abstract|18223843]])=== |
| Line 324: |
Line 128: |
| | Sanjay Subbarao | | Sanjay Subbarao |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a processing device that receives a request for a host-initiated operation on a specific part of a memory device.
| |
| − | * The processing device uses a second L2P table to map logical addresses to physical addresses in a different part of the memory device.
| |
| − | * The second L2P table helps identify the physical location within the memory device corresponding to the logical address.
| |
| − | * This physical location corresponds to a portion of a first L2P table that specifies the physical address within the desired part of the memory device.
| |
| − | * The processing device then performs the host-initiated operation at the identified physical address.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A processing device receives a request specifying a logical address associated with a host-initiated operation directed at a first portion of a memory device. The processing device accesses a second L2P table comprising a mapping between logical addresses and physical addresses in a second portion of the memory device. A physical location within the second portion of the memory device is identified based on the second L2P table. The physical location corresponds to a portion of a first L2P table that specifies a physical address within the first portion of the memory device that corresponds to the logical address. The physical address is identified based on the portion of the first L2P table and the host-initiated operation is performed at the physical address.
| |
| | | | |
| | ===PULSE BASED MULTI-LEVEL CELL PROGRAMMING ([[US Patent Application 17740069. PULSE BASED MULTI-LEVEL CELL PROGRAMMING simplified abstract|17740069]])=== | | ===PULSE BASED MULTI-LEVEL CELL PROGRAMMING ([[US Patent Application 17740069. PULSE BASED MULTI-LEVEL CELL PROGRAMMING simplified abstract|17740069]])=== |
| Line 342: |
Line 136: |
| | Hernan A. Castro | | Hernan A. Castro |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | - This patent application describes methods, systems, and devices for programming multi-level memory cells using pulse-based techniques.
| |
| − | - The memory device can identify an intermediate logic state to be stored in a multi-level memory cell that can store three or more logic states.
| |
| − | - To store a SET or RESET state in the memory cell, the memory device applies a first pulse with a first polarity based on the identified intermediate logic state.
| |
| − | - The memory device also identifies the threshold voltage of the memory cell that stores the SET or RESET state.
| |
| − | - To store the identified intermediate logic state, the memory device applies a quantity of pulses to the memory cell, which may have a second polarity different from the first polarity.
| |
| − | - This technique allows for efficient programming of multi-level memory cells, enabling the storage of multiple logic states in a single cell.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Methods, systems, and devices for pulse based multi-level cell programming are described. A memory device may identify an intermediate logic state to store to a multi-level memory cell capable of storing three or more logic states. The memory device may apply a first pulse with a first polarity to the memory cell to store a SET or RESET state to the memory cell based on identifying the intermediate logic state. As such, the memory device may identify a threshold voltage of the memory cell that stores the SET or RESET state. The memory device may apply a quantity of pulses to the memory cell to store the identified intermediate logic state based on identifying the threshold voltage of the memory cell that stores the SET or RESET state. In some examples, the quantity of pulses may have a second polarity different than the first polarity.
| |
| | | | |
| | ===TECHNIQUES TO MITIGATE MEMORY DIE MISALIGNMENT ([[US Patent Application 17629600. TECHNIQUES TO MITIGATE MEMORY DIE MISALIGNMENT simplified abstract|17629600]])=== | | ===TECHNIQUES TO MITIGATE MEMORY DIE MISALIGNMENT ([[US Patent Application 17629600. TECHNIQUES TO MITIGATE MEMORY DIE MISALIGNMENT simplified abstract|17629600]])=== |
| Line 361: |
Line 144: |
| | Jie Yang | | Jie Yang |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes methods, systems, and devices for mitigating memory die misalignment.
| |
| − | * Memory systems may receive commands to write data to a memory device.
| |
| − | * The system determines if the data satisfies a threshold size.
| |
| − | * If the data satisfies the threshold size, the system checks if the data in the write buffer aligns with the boundary of the memory die.
| |
| − | * Adding the data to the buffer may result in die misalignment.
| |
| − | * To mitigate die misalignment, the system pads the data in the write buffer with dummy data.
| |
| − | * The padding aligns the data with the die boundary.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Methods, systems, and devices for mitigating memory die misalignment are described. A memory system may receive a command to write data to a memory device including a memory die. The memory system may determine whether the data indicated by the command (e.g., a first set of data) satisfies a threshold size. If the first set of data satisfies the threshold size, the memory system may determine whether data currently in a write buffer aligns with a boundary of the memory die. For example, depending on the data currently in the buffer, adding the first set of data to the buffer may result in die misalignment for the first set of data. To mitigate die misalignment, the memory system may pad data (e.g., add dummy data) to the write buffer, such that the padding aligns the data with the die boundary.
| |
| | | | |
| | ===SEMICONDUCTOR DEVICE HAVING POWER CONTROL CIRCUIT ([[US Patent Application 17740200. SEMICONDUCTOR DEVICE HAVING POWER CONTROL CIRCUIT simplified abstract|17740200]])=== | | ===SEMICONDUCTOR DEVICE HAVING POWER CONTROL CIRCUIT ([[US Patent Application 17740200. SEMICONDUCTOR DEVICE HAVING POWER CONTROL CIRCUIT simplified abstract|17740200]])=== |
| Line 381: |
Line 152: |
| | Kazuhiro Yoshida | | Kazuhiro Yoshida |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes an apparatus that includes a semiconductor substrate with source and drain regions, as well as gate electrodes.
| |
| − | * The apparatus has a semiconductor substrate with source and drain regions, which are connected to power supply lines.
| |
| − | * The first drain region is positioned between the first and second source regions, while the second source region is positioned between the first and second drain regions.
| |
| − | * The gate electrodes consist of a first gate electrode between the first source and drain regions, a second gate electrode between the first drain and second source regions, and a third gate electrode between the second source and drain regions.
| |
| − | * The first and third gate electrodes are supplied with a first control signal, while the second gate electrode is supplied with a second control signal.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Disclosed herein is an apparatus that includes: a semiconductor substrate including first and second source regions coupled to a first power supply line and first and second drain regions coupled to a second power supply line, the first drain region being arranged between the first and second source regions, the second source region being arranged between the first and second drain regions; and gate electrodes including a first gate electrode arranged between the first source region and the first drain region, a second gate electrode arranged between the first drain region and the second source region, and a third gate electrode arranged between the second source region and the second drain region. The first and third gate electrodes are supplied with a first control signal. The second gate electrode is supplied with a second control signal.
| |
| | | | |
| | ===APPARATUSES AND METHODS FOR COMPENSATED SENSE AMPLIFIER WITH CROSS COUPLED N-TYPE TRANSISTORS ([[US Patent Application 17662198. APPARATUSES AND METHODS FOR COMPENSATED SENSE AMPLIFIER WITH CROSS COUPLED N-TYPE TRANSISTORS simplified abstract|17662198]])=== | | ===APPARATUSES AND METHODS FOR COMPENSATED SENSE AMPLIFIER WITH CROSS COUPLED N-TYPE TRANSISTORS ([[US Patent Application 17662198. APPARATUSES AND METHODS FOR COMPENSATED SENSE AMPLIFIER WITH CROSS COUPLED N-TYPE TRANSISTORS simplified abstract|17662198]])=== |
| Line 399: |
Line 160: |
| | Jiyun Li | | Jiyun Li |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes an apparatus, system, and method for a compensated sense amplifier with crosscoupled n-type transistors.
| |
| − |
| |
| − | * The sense amplifier includes a pair of p-type transistors that are connected between a system voltage and two gut nodes.
| |
| − | * When a command signal is active, the p-type transistors are connected in a diode fashion from the system voltage to the respective gut nodes.
| |
| − | * The amplifier also includes a pair of n-type transistors that are cross coupled.
| |
| − | * The first n-type transistor has a node connected to the first gut node and a gate connected to the second gut node.
| |
| − | * The second n-type transistor has a node connected to the second gut node and a gate connected to the first gut node.
| |
| − | * Each of the n-type transistors may have a separate current flowing through them.
| |
| − | * There is also a pair of feedback transistors that connect to a ground voltage.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Apparatuses, systems, and methods for compensated sense amplifier with crosscoupled n-type transistors. A sense amplifier has a pair of p-type transistors coupled between a system voltage and respective first and second gut nodes. When a command signal is active, the p-type transistors are coupled in a diode fashion from the system voltage to the respective gut nodes. The amplifier also has a pair of n-type transistors which are cross coupled, where a first n-type transistor has a node coupled to the first gut node and a gate coupled to the second gut node and the second n-type transistor has a node coupled to the second gut node and a gate coupled to the first gut node. Each of the n-type transistors may have a separate current flowing through them and respective one of a pair of feedback transistors to a ground voltage.
| |
| | | | |
| | ===APPARATUSES FOR SENSE AMPLIFIER VOLTAGE CONTROL ([[US Patent Application 17737999. APPARATUSES FOR SENSE AMPLIFIER VOLTAGE CONTROL simplified abstract|17737999]])=== | | ===APPARATUSES FOR SENSE AMPLIFIER VOLTAGE CONTROL ([[US Patent Application 17737999. APPARATUSES FOR SENSE AMPLIFIER VOLTAGE CONTROL simplified abstract|17737999]])=== |
| Line 421: |
Line 168: |
| | Sang-Kyun Park | | Sang-Kyun Park |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes apparatuses that include a level shifter circuit.
| |
| − | * The apparatus includes multiple array access control circuits and a level shifter circuit.
| |
| − | * The array access control circuits receive an access control signal and section enable signals.
| |
| − | * When a section enable signal is active, an array access control circuit provides a section access control signal in response to the access control signal.
| |
| − | * The level shifter circuit receives a control signal and provides an access control signal based on the first signal.
| |
| − | * The control signal has a first logic level represented by a first power supply voltage.
| |
| − | * The access control signal has a first logic level represented by a second power supply voltage, which is greater than the first power supply voltage.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Apparatuses including a level shifter circuit are disclosed. An example apparatus according to the disclosure includes a plurality of array access control circuits and a level shifter circuit. The plurality of array access control circuits receive an access control signal and a respective plurality of section enable signals. An array access control circuit of the plurality of array access control circuits provides a section access control signal responsive to the access control signal when a respective section enable signal is in an active state. The level shifter circuit receives a control signal and provides an access control signal responsive to the first signal. A first logic level of the control signal is represented by a first power supply voltage and a first logic level of the access control signal is represented by a second power supply voltage greater than the first power supply voltage.
| |
| | | | |
| | ===CORRECTIVE READS WITH IMPROVED RECOVERY FROM DATA RETENTION LOSS ([[US Patent Application 18142112. CORRECTIVE READS WITH IMPROVED RECOVERY FROM DATA RETENTION LOSS simplified abstract|18142112]])=== | | ===CORRECTIVE READS WITH IMPROVED RECOVERY FROM DATA RETENTION LOSS ([[US Patent Application 18142112. CORRECTIVE READS WITH IMPROVED RECOVERY FROM DATA RETENTION LOSS simplified abstract|18142112]])=== |
| Line 441: |
Line 176: |
| | Huai-Yuan Tseng | | Huai-Yuan Tseng |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a method for reading a target cell in a memory system.
| |
| − | * The method involves obtaining state information for two adjacent cells next to the target cell.
| |
| − | * A state information bin is determined by applying a predefined operation to the state information of the adjacent cells.
| |
| − | * The target cell is then assigned to the state information bin.
| |
| − | * Each state information bin defines a read level offset, which is used to read the target cell.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A read is initiated with respect to a target cell. A pair of adjacent cells includes a first cell and a second cell each adjacent to the target cell. First cell state information is obtained for the first cell and second cell state information is obtained for the second cell. A state information bin is determined by applying a pre-defined operation to the first cell state information and the second cell state information of the respective pair of adjacent cells. The target cell is assigned to the state information bin. Each state information bin defines a read level offset for reading the target cell.
| |
| | | | |
| | ===TECHNIQUES FOR MULTI-LEVEL MEMORY CELL PROGRAMMING ([[US Patent Application 17740062. TECHNIQUES FOR MULTI-LEVEL MEMORY CELL PROGRAMMING simplified abstract|17740062]])=== | | ===TECHNIQUES FOR MULTI-LEVEL MEMORY CELL PROGRAMMING ([[US Patent Application 17740062. TECHNIQUES FOR MULTI-LEVEL MEMORY CELL PROGRAMMING simplified abstract|17740062]])=== |
| Line 459: |
Line 184: |
| | Innocenzo Tortorelli | | Innocenzo Tortorelli |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes improved techniques for programming multi-level memory cells.
| |
| − | * The memory array receives a command to store a logic state in a memory cell capable of storing three or more logic states.
| |
| − | * An erase operation is performed by applying a pulse with a certain polarity to multiple memory cells, including the target memory cell, to store a different logic state in them.
| |
| − | * A write operation or an erase operation involves applying one or more pulses with a different polarity to the memory cell to store the desired logic state based on the initial pulse applied during the erase operation.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Methods, systems, and devices for improved techniques for multi-level memory cell programming are described. A memory array may receive a first command to store a first logic state in a memory cell for storing three or more logic states. The memory array may apply, as part of an erase operation, a first pulse with a first polarity to a plurality of memory cells to store a second logic state different from the first logic state in the plurality of memory cells, where the plurality of memory cells includes the memory cell. The memory array may apply, as part of a write operation or as part of the erase operation, one or more second pulses with a second polarity to the memory cell to store the first logic state in the memory cell based on applying the first pulse.
| |
| | | | |
| | ===PARTIAL BLOCK HANDLING IN A NON-VOLATILE MEMORY DEVICE ([[US Patent Application 17739741. PARTIAL BLOCK HANDLING IN A NON-VOLATILE MEMORY DEVICE simplified abstract|17739741]])=== | | ===PARTIAL BLOCK HANDLING IN A NON-VOLATILE MEMORY DEVICE ([[US Patent Application 17739741. PARTIAL BLOCK HANDLING IN A NON-VOLATILE MEMORY DEVICE simplified abstract|17739741]])=== |
| Line 476: |
Line 192: |
| | Zhongguang Xu | | Zhongguang Xu |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a protocol for handling a closed block of memory in a processing device's memory sub-system.
| |
| − | * The protocol involves programming wordlines in the memory block with specific data patterns.
| |
| − | * The processing device sends a first programming command to program adjacent wordlines with first padding data.
| |
| − | * The first padding data has a specific data pattern.
| |
| − | * The processing device also sends a second programming command to program the remaining wordlines with second padding data.
| |
| − | * The second padding data has a different data pattern with fewer bits of data per cell than the first padding data.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.
| |
| | | | |
| | ===MEMORY PROGRAMMING USING CONSECUTIVE COARSE-FINE PROGRAMMING OPERATIONS OF THRESHOLD VOLTAGE DISTRIBUTIONS ([[US Patent Application 18138551. MEMORY PROGRAMMING USING CONSECUTIVE COARSE-FINE PROGRAMMING OPERATIONS OF THRESHOLD VOLTAGE DISTRIBUTIONS simplified abstract|18138551]])=== | | ===MEMORY PROGRAMMING USING CONSECUTIVE COARSE-FINE PROGRAMMING OPERATIONS OF THRESHOLD VOLTAGE DISTRIBUTIONS ([[US Patent Application 18138551. MEMORY PROGRAMMING USING CONSECUTIVE COARSE-FINE PROGRAMMING OPERATIONS OF THRESHOLD VOLTAGE DISTRIBUTIONS simplified abstract|18138551]])=== |
| Line 495: |
Line 200: |
| | Huai-Yuan Tseng | | Huai-Yuan Tseng |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a method for programming memory cells in a memory array.
| |
| − | * The method involves programming a first set of memory cells with a first set of threshold voltage distributions.
| |
| − | * A second set of memory cells, adjacent to the first set, is programmed with a second set of threshold voltage distributions.
| |
| − | * After programming the second set of cells, the first set of memory cells is coarse programmed with an intermediate third set of threshold voltage distributions, which is twice in number compared to the first set.
| |
| − | * The first set of memory cells is then fine programmed with a final third set of threshold voltage distributions.
| |
| − | * Some threshold voltage distributions in the final set have wider read window margins compared to the intermediate set.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A method includes causing a first set of memory cells, associated with a first wordline of a memory array, to be programmed with a first set of threshold voltage distributions; causing a second set of memory cells, associated with a second wordline adjacent to the first wordline, to be programmed with a second set of threshold voltage distributions; after programming the second set of cells, causing the first set of memory cells to be coarse programmed with an intermediate third set of threshold voltage distributions that is at least twice in number compared to the first set; and causing the first set of memory cells to be fine programmed with a final third set of threshold voltage distributions. At least some threshold voltage distributions of the final third set of threshold voltage distributions have wider read window margins than those of the intermediate third set of threshold voltage distributions.
| |
| | | | |
| | ===MEMORY SYSTEMS WITH FLEXIBLE ERASE SUSPEND-RESUME OPERATIONS, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS ([[US Patent Application 17739789. MEMORY SYSTEMS WITH FLEXIBLE ERASE SUSPEND-RESUME OPERATIONS, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS simplified abstract|17739789]])=== | | ===MEMORY SYSTEMS WITH FLEXIBLE ERASE SUSPEND-RESUME OPERATIONS, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS ([[US Patent Application 17739789. MEMORY SYSTEMS WITH FLEXIBLE ERASE SUSPEND-RESUME OPERATIONS, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS simplified abstract|17739789]])=== |
| Line 514: |
Line 208: |
| | Pitamber Shukla | | Pitamber Shukla |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | - The patent application describes memory systems with flexible erase suspend-resume operations.
| |
| − | - The memory device can receive an erase suspend command during an erase operation.
| |
| − | - When the erase suspend command is received, the memory device suspends the erase operation.
| |
| − | - The memory device then resumes the erase operation by ramping the voltage to the flattop level for the second erase pulse.
| |
| − | - Without any erase suspend operations, the memory device can perform a single erase pulse that remains at the flattop voltage for a total duration.
| |
| − | - The total duration of the first and second erase pulses, when combined, is less than or equal to the total duration of the single erase pulse.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Memory systems with flexible erase suspend-resume operations are described herein. In one embodiment, a memory device is configured to receive an erase suspend command while a first erase pulse of an erase operation is at a flattop voltage. In response, the memory device suspends the erase operation. The memory device further resumes the erase operation such that a second erase pulse of the erase operation is ramped to the flattop voltage. Absent intervening erase suspend operations, erase operations of the memory device can include a single erase pulse that remains at the flattop voltage for a total duration. A first total duration plus a second total duration the first and second erase pulses, respectively, remain at the flattop voltage remains less than or equal to the total duration the single erase pulse remains at the flattop voltage.
| |
| | | | |
| | ===MANAGING SUB-BLOCK ERASE OPERATIONS IN A MEMORY SUB-SYSTEM ([[US Patent Application 18224179. MANAGING SUB-BLOCK ERASE OPERATIONS IN A MEMORY SUB-SYSTEM simplified abstract|18224179]])=== | | ===MANAGING SUB-BLOCK ERASE OPERATIONS IN A MEMORY SUB-SYSTEM ([[US Patent Application 18224179. MANAGING SUB-BLOCK ERASE OPERATIONS IN A MEMORY SUB-SYSTEM simplified abstract|18224179]])=== |
| Line 533: |
Line 216: |
| | Kalyan Chakravarthy Kavalipurapu | | Kalyan Chakravarthy Kavalipurapu |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a processing device in a memory system that connects two data blocks in order to generate a combined data block.
| |
| − | * The connecting process involves creating a wordline connection between corresponding wordlines of the two data blocks.
| |
| − | * The wordlines are used to drive the data in the memory device.
| |
| − | * The connection is made using a single string driver, which simplifies the process.
| |
| − | * This innovation allows for the efficient combination of data from different blocks in a memory device.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A processing device in a memory system connects a first data block of the memory device to a second data block of the memory device to generate a combined data block comprising a first plurality of sub-blocks of the first data block and a second plurality of sub-blocks of the second data block, wherein the connecting includes: for each wordline of a first plurality of wordlines of the first data block, creating a wordline connection short between the respective wordline of the first data block and a corresponding wordline of a second plurality of wordlines of the second data block, wherein the first plurality of wordlines and the second plurality of wordlines comprise data wordlines; and driving a first data wordline of the first data block and a second wordline of the second data block using a single string driver of the memory device.
| |
| | | | |
| | ===REDUCING PROGRAMMING DISTURBANCE IN MEMORY DEVICES ([[US Patent Application 18195181. REDUCING PROGRAMMING DISTURBANCE IN MEMORY DEVICES simplified abstract|18195181]])=== | | ===REDUCING PROGRAMMING DISTURBANCE IN MEMORY DEVICES ([[US Patent Application 18195181. REDUCING PROGRAMMING DISTURBANCE IN MEMORY DEVICES simplified abstract|18195181]])=== |
| Line 551: |
Line 224: |
| | Aaron Yip | | Aaron Yip |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | - The patent application describes a method for programming memory cells in a block of memory cells.
| |
| − | - During the first portion of the programming operation, the channel material of a string of memory cells in an unselected sub-block is precharged to a precharge voltage.
| |
| − | - During the second portion of the programming operation, a programming voltage is applied to a selected memory cell in a selected sub-block.
| |
| − | - The selected memory cell is connected to the same access line as an unselected memory cell in the unselected sub-block.
| |
| − | - The patent application also discloses additional methods and apparatus related to this programming technique.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then be applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are disclosed.
| |
| | | | |
| | ===ERROR CHECK FUNCTIONALITY VERIFICATION USING KNOWN ERRORS ([[US Patent Application 17738600. ERROR CHECK FUNCTIONALITY VERIFICATION USING KNOWN ERRORS simplified abstract|17738600]])=== | | ===ERROR CHECK FUNCTIONALITY VERIFICATION USING KNOWN ERRORS ([[US Patent Application 17738600. ERROR CHECK FUNCTIONALITY VERIFICATION USING KNOWN ERRORS simplified abstract|17738600]])=== |
| Line 569: |
Line 232: |
| | Francesco Lupo | | Francesco Lupo |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes methods, systems, and apparatuses for error check functionality in a memory device that stores encoded data.
| |
| − | * The memory device receives a request from a host for error check functionality.
| |
| − | * The encoded data is written to a verification portion of the memory device with intentional errors.
| |
| − | * In response to the request, a read command is initiated on the verification portion.
| |
| − | * Based on the result of the read command and the number of intentional errors in the encoded data, an error check functionality indicator is determined.
| |
| − | * The error check functionality indicator corresponding to the number of intentional errors is sent back to the host.
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| − |
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| − | '''Abstract'''
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| − | Methods, systems, and apparatuses include receiving, from a host, an error check functionality request for a memory device that stores encoded data. The encoded data is written to a verification portion of memory with at least one intentional error. A read command of the verification portion is initiated in response to the request. An error check functionality indicator is determined based on a result of the read command and a number of intentional errors in the encoded data. The error check functionality indicator corresponding to the number intentional errors in the encoded data is sent to the host.
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| | ===SELF-REPAIR VERIFICATION ([[US Patent Application 17735528. SELF-REPAIR VERIFICATION simplified abstract|17735528]])=== | | ===SELF-REPAIR VERIFICATION ([[US Patent Application 17735528. SELF-REPAIR VERIFICATION simplified abstract|17735528]])=== |
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| | Takuya Tamano | | Takuya Tamano |
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| − |
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| − | '''Brief explanation'''
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| − | - This patent application describes methods, systems, and devices for self-repair verification in a memory system.
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| − | - The memory system receives a command to initiate a repair operation, which involves replacing a first row of memory cells with a second row of memory cells.
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| − | - The memory system writes first data to the second row of memory cells and reads second data from the second row of memory cells.
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| − | - The memory system uses a stored indication associated with the replacement of rows to determine if the repair operation was successful.
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| − | - If the second data matches the first data, the memory device outputs an error flag with a first value indicating that the repair operation was successfully performed.
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| − |
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| − | '''Abstract'''
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| − | Methods, systems, and devices for self-repair verification are described. A memory system may receive, at a memory device, a command to initiate a repair operation. The memory system may perform the repair operation by replacing a first row of memory cells of the memory device with a second row of memory cells of the memory device. The memory system may write first data to the second row of memory cells, and read second data from the second row of memory cells, based on a stored indication associated with the replacement of rows. The memory device may output an error flag with a first value based at least in part on reading the second data, and the first value of the error flag may indicate that the repair operation was successfully performed based at least in part on the second data matching the first data.
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| | ===MICROELECTRONIC DEVICES INCLUDING VERTICAL INVERTERS, AND ELECTRONIC SYSTEMS ([[US Patent Application 17661979. MICROELECTRONIC DEVICES INCLUDING VERTICAL INVERTERS, AND ELECTRONIC SYSTEMS simplified abstract|17661979]])=== | | ===MICROELECTRONIC DEVICES INCLUDING VERTICAL INVERTERS, AND ELECTRONIC SYSTEMS ([[US Patent Application 17661979. MICROELECTRONIC DEVICES INCLUDING VERTICAL INVERTERS, AND ELECTRONIC SYSTEMS simplified abstract|17661979]])=== |
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| | Kamal M. Karda | | Kamal M. Karda |
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| − |
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| − | '''Brief explanation'''
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| − | The abstract describes a microelectronic device that includes a vertical inverter with a pillar structure.
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| − |
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| − | * The pillar structure is positioned above a first conductive line and includes a first vertical transistor that is connected to the first conductive line.
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| − | * There is also a second conductive line that is vertically positioned above the first conductive line and is isolated from it by a dielectric material.
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| − | * The second conductive line is designed to be connected to a ground structure.
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| − | * Additionally, there is a second vertical transistor that is located next to the first vertical transistor and is connected to the second conductive line.
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| − | * The second vertical transistor is separated from the first vertical transistor by the dielectric material.
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| − | * The device also includes at least one electrode that extends horizontally along the channel regions of both the first and second vertical transistors.
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| − |
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| − | The patent application describes various microelectronic devices and electronic systems that incorporate this vertical inverter structure.
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| − |
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| − | '''Abstract'''
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| − | A microelectronic device comprises vertical inverter comprising a pillar structure vertically extending above a first conductive line. The pillar structure comprises a first vertical transistor vertically overlying and in electrical communication with the first conductive line, a second conductive line vertically overlying the first conductive line and electrically isolated from the first conductive line by a dielectric material, the second conductive line configured to be coupled to a ground structure, a second vertical transistor horizontally neighboring the first vertical transistor and in electrical communication with the second conductive line, the second vertical transistor horizontally spaced from the first vertical transistor by the dielectric material, and at least one electrode horizontally extending along a channel region of the first vertical transistor and an additional channel region of the second vertical transistor. Related microelectronic devices and electronic systems are also described.
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| | | | |
| | ===FINFET ISOLATION DEVICE AND METHOD ([[US Patent Application 17738521. FINFET ISOLATION DEVICE AND METHOD simplified abstract|17738521]])=== | | ===FINFET ISOLATION DEVICE AND METHOD ([[US Patent Application 17738521. FINFET ISOLATION DEVICE AND METHOD simplified abstract|17738521]])=== |
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| | Neng-Kuo Chen | | Neng-Kuo Chen |
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| − |
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| − | '''Brief explanation'''
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| − | The patent application describes an invention related to transistors, memory devices, and systems.
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| − | * The invention includes a structure called an inter-gate dielectric structure, which is placed between adjacent gates.
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| − | * The inter-gate dielectric structure consists of two different dielectric materials.
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| − | * The first dielectric material is located next to a fin channel, while the second dielectric material is placed over the first dielectric material.
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| − | * The purpose of this structure is not explicitly mentioned in the abstract.
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| − |
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| − | '''Abstract'''
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| − | Apparatus and methods are disclosed, including transistors, memory devices and systems. Example transistors, memory devices, systems and methods include an inter-gate dielectric structure between adjacent gates, wherein the inter-gate dielectric structure includes a first dielectric material adjacent a fin channel, and a second dielectric material different from the first dielectric material located over the first dielectric material.
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| | | | |
| | ===HYBRID LOOP UNROLLED DECISION FEEDBACK EQUALIZER ARCHITECTURE ([[US Patent Application 17736802. HYBRID LOOP UNROLLED DECISION FEEDBACK EQUALIZER ARCHITECTURE simplified abstract|17736802]])=== | | ===HYBRID LOOP UNROLLED DECISION FEEDBACK EQUALIZER ARCHITECTURE ([[US Patent Application 17736802. HYBRID LOOP UNROLLED DECISION FEEDBACK EQUALIZER ARCHITECTURE simplified abstract|17736802]])=== |
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| | Jennifer E. Taylor | | Jennifer E. Taylor |
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| − |
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| − | '''Brief explanation'''
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| − | The patent application describes a keeper device used in a hybrid loop unrolled DFE circuit.
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| − | * The keeper device selectively outputs signals from equalizers based on the previous bit value.
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| − | * Equalizers corresponding to different bit possibilities are disabled in the circuit.
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| − | * This saves power when the DFE technique is not used, as only a portion of the equalizers are powered.
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| − |
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| − | '''Abstract'''
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| − | A keeper device is used in a hybrid loop unrolled DFE circuit to selectively output signals from equalizers corresponding to a specific possibility of the values of the previous bit (e.g., logical high or logical low) when DFE technique is not used. Those equalizers corresponding to possibilities other than the specific possibility of the values of the previous bit are disabled in the hybrid loop unrolled DFE circuit. As such, the hybrid loop unrolled DFE circuit saves power when the DFE technique is not used since only a portion of the total equalizers in the hybrid loop unrolled DFE circuit are powered.
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| | | | |
| | ===OPTIMIZATION OF DATA ACCESS AND COMMUNICATION IN MEMORY SYSTEMS ([[US Patent Application 18351991. OPTIMIZATION OF DATA ACCESS AND COMMUNICATION IN MEMORY SYSTEMS simplified abstract|18351991]])=== | | ===OPTIMIZATION OF DATA ACCESS AND COMMUNICATION IN MEMORY SYSTEMS ([[US Patent Application 18351991. OPTIMIZATION OF DATA ACCESS AND COMMUNICATION IN MEMORY SYSTEMS simplified abstract|18351991]])=== |
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| | Parag R. Maharana | | Parag R. Maharana |
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| − |
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| − | '''Brief explanation'''
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| − | - The patent application describes a memory system that includes memory components and a controller.
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| − | - The controller receives access requests from a communication connection.
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| − | - The access requests include data items, addresses of the data items, and contexts of the data items.
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| − | - The controller identifies separate memory regions for different contexts.
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| − | - The data items are placed in the separate memory regions based on their contexts.
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| − | - A mapping is determined between the addresses of the data items and memory locations within the corresponding memory regions.
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| − | - The memory system stores the data items in different memory regions according to their contexts.
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| − |
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| − | '''Abstract'''
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| − | A memory system having one or more memory components and a controller. The controller can receive access requests from a communication connection. The access requests can identify data items associated with the access requests, addresses of the data items, and contexts of the data items in which the data items are used for the access requests. The controller can identify separate memory regions for separate contexts respectively, determine placements of the data items in the separate memory regions based on the contexts of the data items, and determine a mapping between the addresses of the data items and memory locations that are within the separate memory regions corresponding to the contexts of the data items. The memory system stores store the data items at the memory locations separated by different memory regions according to different contexts.
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| | | | |
| | ===SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME ([[US Patent Application 17740064. SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME simplified abstract|17740064]])=== | | ===SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME ([[US Patent Application 17740064. SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME simplified abstract|17740064]])=== |
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| | Yuki Munetaka | | Yuki Munetaka |
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| − |
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| − | '''Brief explanation'''
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| − | The patent application describes an apparatus that includes multiple memory cells arranged in a memory cell array region.
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| − | * The apparatus also includes word lines that extend across both the memory cell array region and a peripheral region where no memory cells are present.
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| − | * Contact plugs are located on the even numbered word lines in the peripheral region.
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| − | * Insulating walls are located on the odd numbered word lines in the peripheral region.
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| − |
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| − | '''Abstract'''
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| − | An apparatus includes a plurality of memory cells in a memory cell array region; a plurality of word lines extending across the memory cell array region and a peripheral region in which no memory cell is arranged; a plurality of contact plugs on even numbered ones of the plurality of word lines in the peripheral region, respectively; and a plurality of insulating walls on odd numbered ones of the plurality of word lines in the peripheral region, respectively.
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| | | | |
| | ===Integrated Circuitry And Method Used In Forming A Memory Array Comprising Strings Of Memory Cells ([[US Patent Application 18218496. Integrated Circuitry And Method Used In Forming A Memory Array Comprising Strings Of Memory Cells simplified abstract|18218496]])=== | | ===Integrated Circuitry And Method Used In Forming A Memory Array Comprising Strings Of Memory Cells ([[US Patent Application 18218496. Integrated Circuitry And Method Used In Forming A Memory Array Comprising Strings Of Memory Cells simplified abstract|18218496]])=== |
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| | | | |
| | John D. Hopkins | | John D. Hopkins |
| − |
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| − |
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| − | '''Brief explanation'''
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| − | The patent application describes an integrated circuit with a memory array that includes strings of memory cells.
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| − | * The memory cells are made up of laterally-spaced memory blocks, each containing a vertical stack of alternating insulative and conductive tiers.
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| − | * The conductive tiers have horizontally-elongated conductive lines.
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| − | * The memory cells also have channel-material strings that extend through the insulative and conductive tiers.
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| − | * The integrated circuit also includes a second vertical stack next to the first one.
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| − | * The second vertical stack has an upper portion with alternating insulating tiers and a lower portion with a lowest insulator tier made of solid carbon and nitrogen-containing material.
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| − | * There is an immediately-adjacent tier above the lowest insulator tier, made of a different composition.
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| − | * The patent application also mentions other embodiments and methods related to the invention.
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| − |
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| − | '''Abstract'''
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| − | Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks that individually comprise a first vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an upper portion and a lower portion. The upper portion comprises alternating first insulating tiers and second insulating tiers. The lower portion comprises a lowest insulator tier directly above conductor material of a conductor tier. The lowest insulator tier comprises solid carbon and nitrogen-containing material. An immediately-adjacent tier is directly above the solid carbon and nitrogen-containing material of the lowest insulator tier. The immediately-adjacent tier comprises material that is of different composition from that of the lowest insulator tier. Other embodiments, including methods, are disclosed.
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