US Patent Application 17633525. MEMORY WRITE PERFORMANCE TECHNIQUES simplified abstract

From WikiPatents
Jump to navigation Jump to search

MEMORY WRITE PERFORMANCE TECHNIQUES

Organization Name

Micron Technology, Inc.


Inventor(s)

Bin Zhao of Shanghai (CN)

Jonathan S. Parry of Boise ID (US)

Deping He of Boise ID (US)

Xu Zhang of Shanghai (CN)

MEMORY WRITE PERFORMANCE TECHNIQUES - A simplified explanation of the abstract

This abstract first appeared for US patent application 17633525 titled 'MEMORY WRITE PERFORMANCE TECHNIQUES

Simplified Explanation

The patent application describes methods, systems, and devices for improving memory write performance.

  • A memory system receives a sequence of commands from a host system.
  • The memory system analyzes the logical block addresses of the commands to determine their relationship.
  • Based on this relationship, the memory system may delay performing certain memory management operations for a duration.
  • Memory management operations can include garbage collection, power operations, cache synchronization, data relocation, etc.
  • The memory system determines if the quantity of write commands with non-consecutive logical block addresses exceeds a threshold.
  • If the threshold is exceeded, the memory system may perform some commands during the duration.
  • At the end of the duration, the memory system performs the memory management operation.


Original Abstract Submitted

Methods, systems, and devices for memory write performance techniques are described. A memory system may receive a sequence of commands, for example from a host system. Based on a relationship between logical block addresses of the sequence of commands, the memory system may delay performing a memory management operation (e.g., a garbage collection procedure, a power operation, a cache synchronization operation, a data relocation operation, or the like) for a duration. For example, the memory system may determine whether a quantity of write commands in the sequence that include non-consecutive logical block addresses exceeds a threshold. In some cases, the memory system may perform one or more commands in the sequence during the duration. Subsequently (e.g., at the end of the duration), the memory system may perform the memory management operation.