US Patent Application 18224179. MANAGING SUB-BLOCK ERASE OPERATIONS IN A MEMORY SUB-SYSTEM simplified abstract
Contents
MANAGING SUB-BLOCK ERASE OPERATIONS IN A MEMORY SUB-SYSTEM
Organization Name
Inventor(s)
Kalyan Chakravarthy Kavalipurapu of Telangana (IN)
Tomoko Ogura Iwasaki of San Jose CA (US)
Erwin E. Yu of San Jose CA (US)
Hong-Yan Chen of San Jose CA (US)
MANAGING SUB-BLOCK ERASE OPERATIONS IN A MEMORY SUB-SYSTEM - A simplified explanation of the abstract
This abstract first appeared for US patent application 18224179 titled 'MANAGING SUB-BLOCK ERASE OPERATIONS IN A MEMORY SUB-SYSTEM
Simplified Explanation
The abstract describes a processing device in a memory system that connects two data blocks in order to generate a combined data block.
- The connecting process involves creating a wordline connection between corresponding wordlines of the two data blocks.
- The wordlines are used to drive the data in the memory device.
- The connection is made using a single string driver, which simplifies the process.
- This innovation allows for the efficient combination of data from different blocks in a memory device.
Original Abstract Submitted
A processing device in a memory system connects a first data block of the memory device to a second data block of the memory device to generate a combined data block comprising a first plurality of sub-blocks of the first data block and a second plurality of sub-blocks of the second data block, wherein the connecting includes: for each wordline of a first plurality of wordlines of the first data block, creating a wordline connection short between the respective wordline of the first data block and a corresponding wordline of a second plurality of wordlines of the second data block, wherein the first plurality of wordlines and the second plurality of wordlines comprise data wordlines; and driving a first data wordline of the first data block and a second wordline of the second data block using a single string driver of the memory device.
