US Patent Application 17740069. PULSE BASED MULTI-LEVEL CELL PROGRAMMING simplified abstract
Contents
PULSE BASED MULTI-LEVEL CELL PROGRAMMING
Organization Name
Inventor(s)
Hernan A. Castro of Shingle Springs CA (US)
Mattia Boniardi of Cormano (IT)
Innocenzo Tortorelli of Cernusco Sul Naviglio (IT)
PULSE BASED MULTI-LEVEL CELL PROGRAMMING - A simplified explanation of the abstract
This abstract first appeared for US patent application 17740069 titled 'PULSE BASED MULTI-LEVEL CELL PROGRAMMING
Simplified Explanation
- This patent application describes methods, systems, and devices for programming multi-level memory cells using pulse-based techniques. - The memory device can identify an intermediate logic state to be stored in a multi-level memory cell that can store three or more logic states. - To store a SET or RESET state in the memory cell, the memory device applies a first pulse with a first polarity based on the identified intermediate logic state. - The memory device also identifies the threshold voltage of the memory cell that stores the SET or RESET state. - To store the identified intermediate logic state, the memory device applies a quantity of pulses to the memory cell, which may have a second polarity different from the first polarity. - This technique allows for efficient programming of multi-level memory cells, enabling the storage of multiple logic states in a single cell.
Original Abstract Submitted
Methods, systems, and devices for pulse based multi-level cell programming are described. A memory device may identify an intermediate logic state to store to a multi-level memory cell capable of storing three or more logic states. The memory device may apply a first pulse with a first polarity to the memory cell to store a SET or RESET state to the memory cell based on identifying the intermediate logic state. As such, the memory device may identify a threshold voltage of the memory cell that stores the SET or RESET state. The memory device may apply a quantity of pulses to the memory cell to store the identified intermediate logic state based on identifying the threshold voltage of the memory cell that stores the SET or RESET state. In some examples, the quantity of pulses may have a second polarity different than the first polarity.
