US Patent Application 17739741. PARTIAL BLOCK HANDLING IN A NON-VOLATILE MEMORY DEVICE simplified abstract

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PARTIAL BLOCK HANDLING IN A NON-VOLATILE MEMORY DEVICE

Organization Name

Micron Technology, Inc.


Inventor(s)

Zhongguang Xu of San Jose CA (US)

Nicola Ciocchini of Boise ID (US)

Zhenlei Shen of Milpitas CA (US)

Charles See Yeung Kwong of Redwood City CA (US)

Murong Lang of San Jose CA (US)

Ugo Russo of Boise ID (US)

Niccolo' Righetti of Boise ID (US)

PARTIAL BLOCK HANDLING IN A NON-VOLATILE MEMORY DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 17739741 titled 'PARTIAL BLOCK HANDLING IN A NON-VOLATILE MEMORY DEVICE

Simplified Explanation

The patent application describes a protocol for handling a closed block of memory in a processing device's memory sub-system.

  • The protocol involves programming wordlines in the memory block with specific data patterns.
  • The processing device sends a first programming command to program adjacent wordlines with first padding data.
  • The first padding data has a specific data pattern.
  • The processing device also sends a second programming command to program the remaining wordlines with second padding data.
  • The second padding data has a different data pattern with fewer bits of data per cell than the first padding data.


Original Abstract Submitted

A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.

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