Intel Corporation patent applications published on October 26th, 2023

Patent applications for Intel Corporation on October 26th, 2023

CURRENT SENSING IN NON-CMOS SEMICONDUCTOR TECHNOLOGY FOR POWER CONVERSION APPLICATIONS (17727153)

Main Inventor

Nachiket Desai

Brief explanation

The abstract describes a current sensor for a power converter, specifically a buck converter. The power converter is made using a high bandgap semiconductor die, while the current sensor is made using both the same die and a silicon die. The current sensor consists of a sense transistor on the same die and a feedback circuit on the silicon die. The feedback circuit controls the voltage of the sense transistor to ensure it is biased correctly based on the bias of a switching transistor in the power converter. The current of the sense transistor can then be processed using techniques like averaging or sampling.

Abstract

Embodiments herein relate to a current sensor for a power converter such as a buck converter. The power converter is fabricated on a high bandgap semiconductor die while the current sensor includes a portion on the same die and a portion on a silicon die. The portion on the same die includes a sense transistor, while the portion on the silicon die includes a feedback circuit for controlling a voltage of the sense transistor to ensure it is biased according to the bias of a switching transistor of the power converter. A current of the sense transistor can then be processed such as by an averaging or sampling process.

COVERED CAVITY FOR A PHOTONIC INTEGRATED CIRCUIT (PIC) (17725090)

Main Inventor

Chia-Pin Chiu

Brief explanation

The abstract describes a structure for photonic integrated circuits (PICs) that includes a micro-ring resonator (MRR) with a heater. The structure involves creating air cavities in different layers of the circuit, such as an overlaying oxide layer, a buried oxide layer, or an underlying silicon layer. These air cavities can be customized in terms of size, shape, and location to manage heat effectively. A thin film is placed on top of the air cavity to prevent any interference with the performance of silicon waveguides and to prevent underfill from entering the cavity. This structure can be used for multiple MRRs in an array.

Abstract

Covered cavity structure for Photonic integrated circuits (PICs) that include a micro-ring resonator (MRR) with a heater. Air cavities are etched or otherwise thinned into an overlaying oxide layer, a buried oxide layer, or an underlying silicon layer. Variations in size, shape, and location of the covered air cavity associated with an MRR provide customizable options for thermal management. A thin film across an upper surface covers the air cavity, providing a barrier to underfill in the air cavity and preventing interference of underfill with performance of silicon waveguides. When arrayed into a plurality of MRRs, the thin film can cover the plurality of MRRs.

PLASMONIC JUNCTION ON A PACKAGE FOR ENHANCING EVANESCENT COUPLING OF OPTICAL INTERCONNECTS (17729974)

Main Inventor

Brandon C. MARIN

Brief explanation

The abstract describes optical interconnects and methods of creating them. These interconnects involve embedding an optical waveguide in a package substrate. A photonics integrated circuit (PIC) is placed over the substrate, which includes a laser that can be connected to the optical waveguide. Additionally, a plasmonic junction is included between the laser and the optical waveguide.

Abstract

Embodiments disclosed herein include optical interconnects and methods of forming such optical interconnects. In an embodiment, the optical interconnect comprises a package substrate, where an optical waveguide is embedded in the package substrate. In an embodiment, a photonics integrated circuit (PIC) is over the package substrate, where the PIC comprises a laser that is configured to be optically coupled to the optical waveguide. In an embodiment, the optical interconnect further comprises a plasmonic junction between the laser and the optical waveguide.

THERMAL STRUCTURE FOR A MICRO-RING RESONATOR (MRR) IN A PHOTONIC INTEGRATED CIRCUIT (PIC) (17725018)

Main Inventor

Chia-Pin Chiu

Brief explanation

The abstract describes a thermal structure for a type of integrated circuit called an open cavity photonic integrated circuit (OCPIC). This structure includes an air trench that is connected to an air cavity located beneath a component called a micro-ring resonator (MRR). The air trench is a gap in the surrounding oxide material and extends outward from the MRR in a straight line. The structure also has an oxide cladding that is not removed in areas where metal traces and routing are needed. The structure is characterized by having a consistent width along the air trench and a lower diameter at the bottom of the air cavity. In some cases, this lower diameter is the same as the diameter of the air trench.

Abstract

Variations in a thermal structure for an open cavity photonic integrated circuit (OCPIC) having an MRR. The structure includes an air trench in fluid communication with an air cavity that is located under the MRR. The air trench is a gap/opening in the oxide that encircles at least a portion of the MRR and extends outward radially therefrom, with a consistent width, to a diameter D1. An oxide cladding is not removed in areas that are used for metal traces and routing. The structure is characterized by straight walls along the air trench. The structure has a lower diameter D2, measured at a bottom/floor of the air cavity. In various embodiments, D2 is substantially equal to D1.

REAL TIME HOLOGRAPHY USING LEARNED ERROR FEEDBACK (18308447)

Main Inventor

Alexey Supikov

Brief explanation

The abstract discusses techniques for creating holographic images for a heads-up display. These techniques involve using a machine learning model to analyze the target image and generate data. This data is then used to determine a phase pattern through an iterative propagation feedback model. The model calculates a feedback strength value, which is used to generate a phase diffraction pattern for displaying on the holographic plane of the heads-up display.

Abstract

Techniques related to generating holographic images for a holographic heads up display are discussed. Such techniques include application of a machine learning model to the target image to generate data that is used to enable the determination of a phase pattern via an iterative propagation feedback model. The iterative propagation feedback model is used to generate a feedback strength value, which is then used to generate a phase diffraction pattern for presentation at a holographic plane of the heads up display.

METHODS AND APPARATUS FOR AUTONOMOUS MOBILE ROBOTS (18343607)

Main Inventor

Akhilesh S. Thyagaturu

Brief explanation

The abstract describes various systems, devices, and methods related to an autonomous mobile radio access network (RAN) node. The first example apparatus is capable of transmitting a workload to a server, performing local processing of the workload when connectivity with the server is lost, and moving from one location to another. The second example apparatus involves communication of a workload from a client device to a server, determining a better location for the compute device based on network performance, and causing the autonomous mobile RAN node to relocate accordingly.

Abstract

Systems, apparatus, articles of manufacture, and methods are disclosed. A first example apparatus disclosed herein is an autonomous mobile radio access network (RAN) node that includes communication circuitry, instructions, and programmable circuitry to cause the communication circuitry to transmit a workload to a server via a network, initiate local processing of the workload after a loss of connectivity with the server, and move the autonomous mobile RAN node from a first location to a second location. A second example apparatus disclosed herein is an autonomous mobile RAN node that includes communication circuitry, instructions, and programmable circuitry to cause communication of a workload from a client device to a server to process the workload, identify a second location relative to a first location of the compute device based on network performance, and cause the autonomous mobile RAN node to move from the first location to the second location.

METHOD AND APPARATUS TO IMPROVE BANDWIDTH EFFICIENCY IN A DYNAMIC RANDOM ACCESS MEMORY (18215907)

Main Inventor

Todd A. HINCK

Brief explanation

The abstract describes a method to improve the efficiency of accessing data in a type of computer memory called DRAM. The memory array in the DRAM chip is divided into two equal parts, each with multiple banks. Each part is further divided into two equal sub-parts. To access a cache line (a block of data) in the memory array, the first half of the cache line is accessed simultaneously in all the sub-parts. Then, after a certain amount of time, the second half of the cache line is accessed simultaneously in all the sub-parts. This approach helps to reduce the time it takes to access the cache line, thereby improving the overall efficiency of the memory.

Abstract

Bandwidth efficiency is improved by reducing time to access a cache line in a DRAM chip. A memory array in the DRAM chip is internally segmented into two equal size portions, each portion having a plurality of banks. Each respective portion is internally segmented into two equal size sub-portions. A cache line in the memory array is accessed by accessing a first half of the cache line in parallel in all of the sub-portions and accessing a second half of the cache line in parallel in all of the sub-portions of the memory array after a gap time.

INTEGRATED CIRCUITS WITH MACHINE LEARNING EXTENSIONS (18216797)

Main Inventor

Martin Langhammer

Brief explanation

This abstract describes an integrated circuit that has specialized processing blocks optimized for machine learning algorithms. These processing blocks have a multiplier data path that is divided into multiple partial product generators, compressors, and carry-propagate adders. The results from the carry-propagate adders are then added using a floating-point adder. Optionally, the results can be cast to a higher precision. The adder data path includes an adder that combines the results from the floating-point adder with zero, a general-purpose input, or other dot product terms. This specialized processing block greatly increases the functional density for implementing machine learning algorithms.

Abstract

An integrated circuit with specialized processing blocks is provided. A specialized processing block may be optimized for machine learning algorithms and may include a multiplier data path that feeds an adder data path. The multiplier data path may be decomposed into multiple partial product generators, multiple compressors, and multiple carry-propagate adders of a first precision. Results from the carry-propagate adders may be added using a floating-point adder of the first precision. Results from the floating-point adder may be optionally cast to a second precision that is higher or more accurate than the first precision. The adder data path may include an adder of the second precision that combines the results from the floating-point adder with zero, with a general-purpose input, or with other dot product terms. Operated in this way, the specialized processing block provides a technical improvement of greatly increasing the functional density for implementing machine learning algorithms.

METHOD AND APPARATUS FOR HOT UPGRADE OR LIVE RECOVERY OF STORAGE BACKEND SOFTWARE BASED ON IPU OR DPU (18214999)

Main Inventor

Jun ZENG

Brief explanation

This abstract describes methods and devices for upgrading or recovering storage backend software on an Infrastructure Processing Unit (IPU) or Data Processing Unit (DPU) without interrupting the operation of the storage devices. The configuration and queue information related to Input-Output (IO) operations are saved in shared memory. After the upgrade or recovery, the saved information is restored, and IO operations are resumed from the last completed point. The new backend software is also connected to a front-end host driver. The software may use a multi-process model like the Storage Performance Development Kit (SPDK) multi-process model.

Abstract

Methods and apparatus for hot upgrade or live recovery of storage backend software on an IPU (Infrastructure Processing Unit) or DPU (Date Processing Unit). Configuration space and queue related information associated with Input-Output (IO) operations for storage device(s) operatively coupled to the IPU/DPU are saved in shared memory. Following the hot upgrade or live recovery, the configuration space and queue related information are restored and IO operations are restarted at a last completed point prior to initiation of the hot upgrade or live recovery. Additionally, the newly started backend software is reassociated with a front-end host driver. The storage backend software may include instructions for executing primary and secondary processes using a multi-process model such as a Storage Performance Development Kit (SPDK) multi-process model.

APPARATUSES AND METHODS FOR SPECULATIVE EXECUTION SIDE CHANNEL MITIGATION (18138591)

Main Inventor

Jason W. Brandt

Brief explanation

This abstract discusses methods and devices that help prevent speculative execution side channels. It also describes hardware and environments that use these mitigations. The abstract specifically focuses on three mechanisms: indirect branch restricted speculation (IBRS), single thread indirect branch predictors (STIBP), and indirect branch predictor barrier (IBPB). These mechanisms aim to restrict speculation of indirect branches, prevent indirect branch predictions from being controlled by other threads, and prevent software executed before a barrier from controlling indirect branch predictions after the barrier.

Abstract

Methods and apparatuses relating to mitigations for speculative execution side channels are described. Speculative execution hardware and environments that utilize the mitigations are also described. For example, three indirect branch control mechanisms and their associated hardware are discussed herein: (i) indirect branch restricted speculation (IBRS) to restrict speculation of indirect branches, (ii) single thread indirect branch predictors (STIBP) to prevent indirect branch predictions from being controlled by a sibling thread, and (iii) indirect branch predictor barrier (IBPB) to prevent indirect branch predictions after the barrier from being controlled by software executed before the barrier.

METHODS AND APPARATUS TO OPTIMIZE WORKFLOWS (18301755)

Main Inventor

Thijs Metsch

Brief explanation

The abstract describes a technology that optimizes workflows. It includes an apparatus that determines the objective of a user input, creates multiple workflows based on the objective, uses a machine learning model to assign a confidence score to each workflow, and selects the most suitable workflow based on the confidence score for execution in the infrastructure.

Abstract

Methods, apparatus, systems and articles of manufacture are disclosed that optimize workflows. An example apparatus includes an intent determiner to determine an objective of a user input, the objective indicating a task to be executed in an infrastructure, a configuration composer to compose a plurality of workflows based on the determined objective, a model executor to execute a machine learning model to create a confidence score relating to the plurality of workflows, and a workflow selector to select at least one of the plurality of workflows for execution in the infrastructure, the selection of the at least one of the plurality of workflows based on the confidence score.

HARDWARE-BASED GENERATION OF UNCOMPRESSED DATA BLOCKS (18214830)

Main Inventor

Laurent Coquerel

Brief explanation

This abstract describes an accelerator or system that can compress input data. It includes an input interface to receive the input data and user application parameters for compression. The accelerator can identify the compression algorithm based on the configuration data provided with the input data. The user application parameters do not need to specify entropy thresholds for compression. The accelerator generates headers specific to the compression algorithm and creates uncompressed data blocks with headers from the input data. It then determines whether to provide the uncompressed data blocks or compressed data blocks based on the entropy of the input data.

Abstract

An accelerator or system including an accelerator can include an input interface to receive input data to be compressed and user application parameters for invocation of compression. The accelerator can include circuitry to identify a compression algorithm from configuration data provided with the input data. The user application parameters may not include parameters specifying entropy thresholds for compression of the input data. The circuitry can generate headers specific to the compression algorithm. The circuitry can generate uncompressed data blocks comprising blocks of the input data and corresponding headers. The circuitry can determine whether to provide the uncompressed data blocks or compressed data blocks based at least in part on entropy of the input data. Other methods, systems, and apparatuses are described.

METHODS AND APPARATUS FOR A REMOTE PROCESSING ACCELERATION ENGINE (18345497)

Main Inventor

Thomas E. Willis

Brief explanation

The abstract describes a remote processing acceleration engine that includes an infrastructure processing unit (IPU). The IPU has various components such as an offload engine driver, network interface circuitry, and RPC offload circuitry. The offload engine driver allows access to a remote procedure call (RPC) from business logic circuitry. The RPC offload circuitry selects a destination based on its ability to perform the operation using remote direct memory access (RDMA). The network interface circuitry is used to communicate the operation to the selected destination.

Abstract

Systems, apparatus, articles of manufacture, and methods are disclosed for a remote processing acceleration engine. Disclosed is an infrastructure processing unit (IPU) comprising an offload engine driver to access a remote procedure call (RPC) from business logic circuitry, network interface circuitry, and RPC offload circuitry to select a destination to perform an operation associated with the RPC call, the destination selected based on an ability of the destination to perform the operation using remote direct memory access (RDMA), and cause communication of the operation to the destination via the network interface circuitry.

SYSTEM MANAGEMENT MODE (SMM) ERROR HANDLER (17724811)

Main Inventor

Pannerkumar Rajagopal

Brief explanation

This technology involves a processor entering a mode that is not visible to the operating system (OS). When this happens, a flag is set to indicate the entry into this mode, and an identifier (ID) of the error causing the entry is saved. If a system reset is initiated while in this mode, the basic input/output system (BIOS) is booted. During this booting process, an error record is created, which can be accessed by the OS after booting. This error record includes the flag and the error ID. Finally, the OS is booted.

Abstract

The technology describe herein includes upon entering a mode of a processor that is not visible to an operating system (OS), setting a flag indicating entry into the mode and saving an identifier (ID) of an error causing entry into the mode; and responsive to a system reset initiation while in the mode, booting a basic input/output system (BIOS), creating an error record to be accessible to the OS after booting, the error record including the flag and the error ID, and booting the OS.

MULTISYSTEM SHARED MEMORY (18215535)

Main Inventor

Timothy WITHAM

Brief explanation

This abstract describes a system that consists of multiple devices connected to each other through an optical communication link. These devices share a common memory. In this system, some devices act as producers by sending broadcast messages, while others act as consumers by receiving messages from other devices.

When a producer device sends a packet, it holds a lock on a specific portion of the shared memory called a cache line. In response to this packet, the receiving devices send an acknowledgement or negative acknowledgement. They also invalidate the cache line in their local copy of the shared memory, meaning that the data in that cache line is no longer considered valid.

As the devices process data received over the optical communication link, they can update the cache line in their local copy of the shared memory. This allows for efficient sharing and processing of data among the devices in the system.

Abstract

A system includes multiple devices with a shared memory. The devices interconnect to each other via an optical communication link, with broadcast sends as producers, and receiving messages from others as consumers of the other devices. The devices receive a packet from a producer that has a lock on a cache line of the shared memory. In response to the packet, the devices send an acknowledgement or negative acknowledgement, and invalidate the cache line that is the subject of the message in a local copy of the shared memory. The devices can update the cache line in the local copy of the shared memory as data is processed as received over the optical communication link.

Circuit Systems And Methods For Transmitting Signals Between Devices (18216867)

Main Inventor

Md Altaf Hossain

Brief explanation

This abstract describes a circuit system that consists of a support device with two conductors. It also includes three integrated circuits that are connected to the support device. One of the integrated circuits has a peripheral region which has a third conductor that connects the first and second conductors. The circuit system is designed to transmit a signal from the first integrated circuit through the first conductor, the third conductor, and the second conductor to the third integrated circuit. The first and third integrated circuits are positioned diagonally in the circuit system.

Abstract

A circuit system includes a support device that has first and second conductors. The circuit system also includes first, second, and third integrated circuits that are coupled to the support device. The second integrated circuit includes a peripheral region. The peripheral region includes a third conductor coupled between the first and the second conductors. The circuit system is configured to transmit a signal from the first integrated circuit through the first conductor, the third conductor, and the second conductor to the third integrated circuit. The first and the third integrated circuits are positioned diagonally in the circuit system

Systems And Methods For Load Balancing Memory Traffic (18215732)

Main Inventor

Przemek Guzy

Brief explanation

This abstract describes an integrated circuit that has two memory controller circuits and a load balancing multiplexer circuit. The load balancing multiplexer circuit is responsible for redirecting a read operation from the first memory controller circuit to the second memory controller circuit if it detects that the second memory controller circuit has available memory bandwidth. 

In addition, there is a circuit system that includes two memory devices, two memory controller circuits, and the same load balancing multiplexer circuit. This load balancing multiplexer circuit is responsible for sending a write operation to the first memory controller circuit to store data in the first memory device, and also to the second memory controller circuit to store the same data in the second memory device. This circuit system also performs various memory traffic shaping operations.

Abstract

An integrated circuit includes first and second memory controller circuits and a load balancing multiplexer circuit that redirects a first read operation from the first memory controller circuit to the second memory controller circuit in response to receiving an indication that the second memory controller circuit has available memory bandwidth. A circuit system includes first and second memory devices, first and second memory controller circuits, and a load balancing multiplexer circuit that sends a write operation to the first memory controller circuit to store data in the first memory device and to the second memory controller circuit to store the data in the second memory device, while performing a number of memory traffic shaping operations.

Efficient Triangular Systolic Array-Based Matrix Inversion (18217011)

Main Inventor

Tolga Ayhan

Brief explanation

The abstract describes the use of integrated circuit devices to implement a systolic array, which is a type of parallel computing architecture. The circuitry includes processing elements arranged in a triangular systolic array. These processing elements receive an input matrix and perform three stages of operations: Cholesky decomposition, triangular matrix inversion, and matrix multiplication. The result is an output matrix that represents the inverse of the input matrix.

Abstract

Integrated circuit devices, methods, and circuitry for implementing and using a systolic array are provided. Such circuitry may include processing elements arranged in a triangular systolic array. The processing elements may receive an input matrix and perform Cholesky decomposition in a first stage, triangular matrix inversion in a second stage, and matrix multiplication in a third stage to produce an inverse of the input matrix as an output matrix.

HARDWARE ATTESTATION IN A MULTI-NETWORK INTERFACE DEVICE SYSTEM (18215752)

Main Inventor

Eoin WALSH

Brief explanation

The abstract describes a network interface device that has a network interface, processors, and circuitry. This device can be registered and selected as an attestation device by a management controller. Once selected, it can receive attestation information and perform attestation on one or more devices.

Abstract

Examples described herein relate to a network interface device that includes a network interface, one or more processors, and circuitry to: register the network interface device and based on selection as an attestation device by the management controller from among multiple candidate network interface devices, receive attestation information and perform attestation of one or more devices.

LIGHTWEIGHT ELECTRONIC CONTROL UNIT FINGERPRINTING (18215924)

Main Inventor

Eduardo Alban

Brief explanation

This abstract describes systems, devices, and methods that can be used to identify an electronic control unit (ECU) that is transmitting a message on a communication bus, such as a network bus in a vehicle. ECUs transmit messages by manipulating the voltage on the conductive lines of the bus. The system includes observation circuitry that can monitor the voltage signals associated with the transmission at a specific point on the network bus. By analyzing the densities of these voltage signals, a distribution can be generated. This distribution can then be used to identify and/or create a unique fingerprint for each ECU based on its voltage signal patterns.

Abstract

Systems, apparatuses, and methods to identify an electronic control unit transmitting a message on a communication bus, such as an in-vehicle network bus, are provided. ECUs transmit messages by manipulating voltage on conductive lines of the bus. Observation circuitry can observe voltage signals associated with the transmission at a point on the in-vehicle network bus. A distribution can be generated from densities of the voltage signals. ECUs can be identified and/or fingerprinted based on the distributions.

TECHNIQUES TO MITIGATE CACHE-BASED SIDE-CHANNEL ATTACKS (18214870)

Main Inventor

Marcel CORNU

Brief explanation

The abstract discusses various techniques to protect against cache-based side-channel attacks. These attacks involve accessing sensitive data stored in a cache. One approach mentioned is assigning a class of service (COS) to different cores of a process. This helps determine if a potentially malicious application is trying to access a cache line in a processor cache, and alerts the operating system accordingly. Another technique involves marking certain pages in an application's memory address space as unflushable. This prevents a potentially malicious application from accessing sensitive data that is loaded into the processor cache. Overall, these methods aim to mitigate or prevent cache-based side-channel attacks.

Abstract

Examples include techniques to mitigate or prevent cache-based side-channel attacks to a cache. Examples include use of assigned class of service (COS) assigned to cores of a process to determine whether to notify an OS of a potential malicious application attempting to access a cache line cached to a processor cache. Examples also include marking pages in an application memory address space of a processor cache as unflushable to prevent a potentially malicious application from accessing sensitive data loaded to the application memory address space of the processor cache.

PLATFORM SECURITY MECHANISM (18339571)

Main Inventor

Michael Berger

Brief explanation

The abstract describes an apparatus that consists of a computer platform with a central processing unit (CPU) and a chipset. The CPU has a security engine, and the chipset also has a security engine. These security engines work together to establish a secure channel session between the CPU and the chipset. This secure channel ensures that any data transmitted between the CPU and the chipset is protected and secure.

Abstract

An apparatus comprising a computer platform, including a central processing unit (CPU) comprising a first security engine to perform security operations at the CPU and a chipset comprising a second security engine to perform security operations at the chipset, wherein the first security engine and the second security engine establish a secure channel session between the CPU and the chipset to secure data transmitted between the CPU and the chipset.

METHODS AND APPARATUS FOR PROFILE-GUIDED OPTIMIZATION OF INTEGRATED CIRCUITS (18311886)

Main Inventor

Byron Sinclair

Brief explanation

This abstract describes methods and tools for optimizing integrated circuit hardware. Circuit design tools can take source code and compile it into a hardware description. This hardware description includes profiling blocks that measure important information for optimization. The hardware description is then simulated to collect profiling data. The circuit design tools analyze this data to find more opportunities for hardware optimization. Based on this analysis, the source code is modified to create a smaller and faster hardware that is more suitable for the intended application.

Abstract

Methods and apparatus for performing profile-guided optimization of integrated circuit hardware are provided. Circuit design tools may receive a source code and compile the source code to generate a hardware description. The hardware description may include profiling blocks configured to measure useful information required for optimization. The hardware description may then be simulated to gather profiling data. The circuit design tools may then analyze the gathered profiling data to identify additional opportunities for hardware optimization. The source code may then be modified based on the analysis of the profiling data to produce a smaller and faster hardware that is better suited to the application.

LEARNING NEURAL REFLECTANCE SHADERS FROM IMAGES (17849055)

Main Inventor

Benjamin Ummenhofer

Brief explanation

This abstract describes a technique for using machine learning to learn how light interacts with objects in images. The technique involves training a set of machine learning models to optimize the lighting and surface properties of an object based on input images. A shader is then generated using these models, which allows for rendering a 3D representation of the object with realistic lighting and surface appearance.

Abstract

Described herein are techniques for learning neural reflectance shaders from images. A set of one or more machine learning models can be trained to optimize an illumination latent code and a set of reflectance latent codes for an object within a set of input images. A shader can then be generated based on a machine learning model of the one or more machine learning models. The shader is configured to sample the illumination latent code and the set of reflectance latent codes for the object. A 3D representation of the object can be rendered using the generated shader.

CONSTANT-BASED CALCULATIONS IN SHADER PROLOGUE SHARED FUNCTION (18025866)

Main Inventor

Przemyslaw SZYMANSKI

Brief explanation

This abstract describes a system that allows for the efficient execution of shader code in graphics processing. The system creates a single shared function that can be used by multiple instances of a primary shader function. The primary shader function is responsible for computing instance-specific values. The shared function is used to calculate a value that is needed by all instances of the primary shader function. This allows for the graphics execution unit to execute the primary shader function multiple times, while also calling the shared function from within each instance. Overall, this system optimizes the execution of shader code in graphics processing.

Abstract

A system creates a single shared instance of a shared function from shader code for multiple instances of the shader. The system creates multiple instances of a primary shader function from shader code to compute instance-specific values. The system creates the single instance of the shared function to compute a value used by the multiple instances of the primary shader function. A graphics execution unit can execute the multiple instances of the primary shader function, including calling the shared function from the multiple instances of the primary shader function.

ADAPTIVE MULTISAMPLING BASED ON VERTEX ATTRIBUTES (18306668)

Main Inventor

Prasoonkumar Surti

Brief explanation

This abstract describes a technology that determines the anti-aliasing mode for a vertex of a shape based on a specific parameter associated with that vertex. It then generates a coverage mask based on the chosen anti-aliasing mode. The coverage mask is used to shade one or more pixels that correspond to the vertex. It is important to note that the anti-aliasing mode can vary across multiple vertices within the shape.

Abstract

Systems, apparatuses and methods may provide for technology that selects an anti-aliasing mode for a vertex of a primitive based on a parameter associated with the vertex and generates a coverage mask based on the selected anti-aliasing mode. Additionally, one or more pixels corresponding to the vertex may be shaded based at least partly on the coverage mask, wherein the selected anti-aliasing mode varies across a plurality of vertices in the primitive.

INPUT IMAGE SIZE SWITCHABLE NETWORK FOR ADAPTIVE RUNTIME EFFICIENT IMAGE CLASSIFICATION (17918080)

Main Inventor

Anbang YAO

Brief explanation

The abstract discusses various techniques for implementing and training image classification networks. These techniques involve using shared convolutional layers for input images of any resolution and selectively applying normalization based on the image resolution. The abstract also mentions training methods such as mixed image size parallel training and mixed image size ensemble distillation.

Abstract

Techniques related to implementing and training image classification networks are discussed. Such techniques include applying shared convolutional layers to input images regardless of resolution and applying normalization selectively based on the input image resolution. Such techniques further include training using mixed image size parallel training and mixed image size ensemble distillation.

NOR GATE BASED LOCAL ACCESS LINE DESELECT SIGNAL GENERATION (17725384)

Main Inventor

Yasir Mohsin Husain

Brief explanation

The abstract describes a memory device that consists of multiple access lines and memory cells. Each memory cell is connected to a local access line and a global access line. The device also includes signal lines to control select devices that connect the global access lines to the local access lines. Additionally, there is a NOR gate that generates deselect signals to control deselect devices, which connect the local access lines to a deselect voltage.

Abstract

A memory device comprising a plurality of first global access lines, second global access lines, first local access lines, and second local access lines; and a plurality of memory cells, wherein a memory cell is coupled to one of the first local access lines and one of the second local access lines. The memory device further comprises a plurality of signal lines to communicate local access line select signals to control a plurality of select devices, wherein a select device selectively couples one of the first global access lines to one of the first local access lines; and a NOR gate to accept the plurality of local access line select signals as inputs and generate a plurality of local access line deselect signals to control a plurality of deselect devices, wherein a deselect device selectively couples one of the first local access lines to a deselect voltage.

SELF-RESETTING CLOCK GENERATOR (17728256)

Main Inventor

Gururaj Shamanna

Brief explanation

The abstract describes a new clock generator circuit that improves its operation. The circuit includes a clock gate that generates a stable positive clock signal based on various input signals. It also includes two banks of transistors that control the assertion and de-assertion of a clock signal. Additionally, there is a reset circuit that generates a reset signal based on other clock signals. Overall, this new circuit aims to enhance the performance of clock generation in electronic systems.

Abstract

An apparatus, system, and method for improved clock generator circuit operation. A self-resetting clock generator circuit includes a keeper-free clock gate configured to generate a stabilized positive clock (PCLK) signal based on an enable (ENBL) signal, a positive clock (PCLK), a reset (RST) signal, and an external clock (SOC CLK), a first bank of transistors configured to assert a clock signal (ST CLK) based on PCLK, a second bank of transistors in parallel with the first bank of transistors and configured to de-assert (1->0) ST CLK # based on PCLK assertion (0->1), and a logic gate-based reset circuit configured to generate the RST signal based on the SOC CLK and the ST CLK #.

MID-PROCESSING REMOVAL OF SEMICONDUCTOR FINS DURING FABRICATION OF INTEGRATED CIRCUIT STRUCTURES (18216984)

Main Inventor

Mehmet O. BAYKAN

Brief explanation

This abstract describes techniques for creating integrated circuit structures with multiple semiconductor fins, which can be used to create non-planar transistor structures. The techniques involve removing partially-formed fins during the manufacturing process to ensure that the dimensions of the fins are uniform. This is achieved by using a selective etch stop built into the semiconductor structure to partially form the fins, and then removing some of the fins using sacrificial fin cut mask layer(s). After the removal, the process continues by etching trenches between the remaining partially-formed fins to create the transistor channel portion of the fins. A liner material may be added to protect the partially-formed fins during this deep trench etching process.

Abstract

Techniques are disclosed for forming integrated circuit structures having a plurality of semiconductor fins, which in turn can be used to form non-planar transistor structures. The techniques include a mid-process removal of one or more partially-formed fins. The resulting integrated circuit structure includes a plurality of semiconductor fins having relatively uniform dimensions (e.g., fin width and trough depth). In an embodiment, the fin forming procedure includes partially forming a plurality of fins, using a selective etch stop built into the semiconductor structure in which the fins are being formed. One or more of the partially-formed fins are removed via sacrificial fin cut mask layer(s). After fin removal, the process continues by further etching trenches between the partially-formed fins (deep etch) to form portion of fins that will ultimately include transistor channel portion. A liner material may be deposited to protect the partially-formed fins during this subsequent deep trench etch.

SIZE AND EFFICIENCY OF DIES (18216989)

Main Inventor

Mathew J. MANUSHAROW

Brief explanation

The abstract describes an integrated circuit package that includes two integrated circuit dies connected to an organic substrate. The package also includes a multi-die interconnect bridge embedded within the substrate and a termination resistor located within this bridge. The termination resistor is associated with a circuit in one of the integrated circuit dies.

Abstract

An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.

MICROELECTRONIC ASSEMBLIES WITH COMMUNICATION NETWORKS (18216102)

Main Inventor

Adel A. ELSHERBINI

Brief explanation

The abstract describes microelectronic assemblies and related devices and methods. These assemblies consist of a package substrate, a first die connected to the substrate using first interconnects, and a second die connected to the first die using second interconnects. The second die is also connected to the package substrate using third interconnects. The first and second dies contain a communication network, which includes a pathway for communication between them.

Abstract

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

SOLDERED METALLIC RESERVOIRS FOR ENHANCED TRANSIENT AND STEADY-STATE THERMAL PERFORMANCE (18216005)

Main Inventor

Nicholas NEAL

Brief explanation

This abstract describes electronic packages with thermal solutions. The electronic package includes a package substrate, a first die connected to the package substrate, and an integrated heat spreader (IHS) that is thermally connected to the surface of the first die. The IHS consists of a main body with an outer perimeter and one or more legs attached to the outer perimeter, which are supported by the package substrate. Additionally, there is a thermal block between the package substrate and the main body of the IHS, located within the outer perimeter of the main body.

Abstract

Embodiments disclosed herein include electronic packages with thermal solutions. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and an integrated heat spreader (IHS) that is thermally coupled to a surface of the first die. In an embodiment, the IHS comprises a main body having an outer perimeter, and one or more legs attached to the outer perimeter of the main body, wherein the one or more legs are supported by the package substrate. In an embodiment, the electronic package further comprises a thermal block between the package substrate and the main body of the IHS, wherein the thermal block is within the outer perimeter of the main body.

CAPACITOR DIE EMBEDDED IN PACKAGE SUBSTRATE FOR PROVIDING CAPACITANCE TO SURFACE MOUNTED DIE (18214742)

Main Inventor

Andrew COLLINS

Brief explanation

The abstract describes a package substrate that includes a die package located underneath a power delivery interface in a die. The package substrate has connection terminals on its surface that provide connection to the die. Inside the die package, there are metal-insulator-metal layers that are connected to the connection terminals.

Abstract

A package substrate is disclosed. The package substrate includes a die package in the package substrate located at least partially underneath a location of a power delivery interface in a die that is coupled to the surface of the package substrate. Connection terminals are accessible on a surface of the die package to provide connection to the die that is coupled to the surface of the package substrate. Metal-insulator-metal layers inside the die package are coupled to the connection terminals.

MICROELECTRONIC PACKAGE WITH SOLDER ARRAY THERMAL INTERFACE MATERIAL (SA-TIM) (18346321)

Main Inventor

Debendra Mallik

Brief explanation

The abstract describes a microelectronic package that includes a die and a package substrate. The die is connected to the package substrate using solder thermal interface material (STIM) thermal interconnects. An integrated heat spreader (IHS) is also connected to the STIM thermal interconnects. A thermal underfill material is placed between the IHS and the die, surrounding the STIM thermal interconnects. The abstract suggests that there may be other embodiments or variations of this microelectronic package.

Abstract

Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects. Other embodiments may be described or claimed.

FAN OUT PACKAGING POP MECHANICAL ATTACH METHOD (18217000)

Main Inventor

David O'SULLIVAN

Brief explanation

The abstract describes semiconductor packages and a method of creating them. These packages consist of a mold that surrounds a first die and a first via. The package also includes a conductive pad on the top surface of the first die and/or the mold. Additionally, there is a second die with a solder ball attached to a die pad on its bottom surface. This solder ball is connected to the conductive pad of the first die. The first die and second die are connected through a first redistribution layer. The second die is positioned within the footprint of the first die, with one edge inside and the other edge outside the footprint.

Abstract

Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a mold over and around a first die and a first via. The semiconductor package has a conductive pad of a first redistribution layer disposed on a top surface of the first die and/or a top surface of the mold. The semiconductor package includes a second die having a solder ball coupled to a die pad on a bottom surface of the second die, where the solder ball of the second die is coupled to the first redistribution layer. The first redistribution layer couples the second die to the first die, where the second die has a first edge and a second edge, and where the first edge is positioned within a footprint of the first die and the second edge is positioned outside the footprint of the first die.

PACKAGING ARCHITECTURE FOR WAFER-SCALE KNOWN-GOOD-DIE TO KNOWN-GOOD-DIE HYBRID BONDING (17728147)

Main Inventor

Omkar G. Karhade

Brief explanation

The abstract describes a microelectronic assembly that consists of multiple layers connected by fusion bonds. The assembly includes a package substrate attached to the first layer, which contains one or more dies (small chips). The second layer in the stack also contains one or more dies and is connected to the first layer. Between the adjacent surfaces of the dies in either layer, there is a copper lining that covers and contacts these surfaces. The dies can be either dummy dies (without any functioning circuits) or integrated circuit (IC) dies with functional circuits.

Abstract

Embodiments of a microelectronic assembly comprise a microelectronic assembly, comprising: a stack of layers coupled by at least fusion bonds; a package substrate coupled to a first layer in the stack of layers; one or more dies in the first layer; and one or more dies in a second layer in the stack of layers, the second layer coupled to the first layer, wherein: a copper lining is between adjacent surfaces of any two adjacent dies in at least one of the first layer and the second layer, and the copper lining contacts and substantially covers the adjacent surfaces. In various embodiments, the dies comprise dummy dies and integrated circuit (IC) dies, the dummy dies are one of: semiconductor dies without any ICs, and semiconductor dies having non-functional ICs, and the IC dies comprise semiconductor dies having functional ICs.

TECHNIQUES FOR DIE TILING (18216275)

Main Inventor

Srinivas PIETAMBARAM

Brief explanation

This abstract describes techniques for creating fine node heterogeneous-chip packages. The method involves connecting the electrical terminals of two base dies using a silicon bridge, and then forming an organic substrate around the bridge and adjacent to the base dies. Finally, a fine node die is connected to the second side of one of the base dies.

Abstract

Techniques are provided for fine node heterogeneous-chip packages. In an example, a method of making a heterogeneous-chip package can include coupling electrical terminals of a first side of a first base die to electrical terminals of a first side of a second base die using a silicon bridge, forming an organic substrate about the silicon bridge and adjacent the first sides of the first and second base dies, and coupling a fine node die to a second side of at least one of the first base die or the second base die.

INTEGRATED CIRCUIT STRUCTURES WITH SOURCE OR DRAIN DOPANT DIFFUSION BLOCKING LAYERS (18216563)

Main Inventor

Cory BOMBERGER

Brief explanation

This abstract describes integrated circuit structures that have source or drain dopant diffusion blocking layers. These structures include a fin made of silicon, a gate structure over the channel region of the fin, and source or drain structures on either side of the gate structure. The source or drain structures consist of two semiconductor layers - a first layer in contact with the fin's channel region and a second layer on top of the first layer. The first layer has a higher concentration of germanium than the second layer, and the second layer contains boron dopant impurity atoms. These structures help prevent the diffusion of dopant atoms from the source or drain regions into the channel region, improving the performance and reliability of the integrated circuits.

Abstract

Embodiments of the disclosure include integrated circuit structures having source or drain dopant diffusion blocking layers. In an example, an integrated circuit structure includes a fin including silicon. A gate structure is over a channel region of the fin, the gate structure having a first side opposite a second side. A first source or drain structure is at the first side of the gate structure. A second source or drain structure is at the second side of the gate structure. The first and second source or drain structures include a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is in contact with the channel region of the fin, and the second semiconductor layer is on the first semiconductor layer. The first semiconductor layer has a greater concentration of germanium than the second semiconductor layer, and the second semiconductor layer includes boron dopant impurity atoms.

MICROELECTRONIC DEVICES DESIGNED WITH MOLD PATTERNING TO CREATE PACKAGE-LEVEL COMPONENTS FOR HIGH FREQUENCY COMMUNICATION SYSTEMS (18216282)

Main Inventor

Feras EID

Brief explanation

The abstract describes a microelectronic device that consists of two substrates. The first substrate contains radio frequency components, while the second substrate is connected to the first substrate and includes a conductive layer for transmitting and receiving communications at a frequency of 4 GHz or higher. A dielectric material is placed between the two conductive layers of the antenna unit to capacitively couple them.

Abstract

Embodiments of the invention include a microelectronic device that includes a first substrate having radio frequency (RF) components and a second substrate that is coupled to the first substrate. The second substrate includes a first conductive layer of an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher. A mold material is disposed on the first and second substrates. The mold material includes a first region that is positioned between the first conductive layer and a second conductive layer of the antenna unit with the mold material being a dielectric material to capacitively couple the first and second conductive layers of the antenna unit.

METHODS AND APPARATUS TO AUTONOMOUSLY IMPLEMENT POLICIES AT THE EDGE (18344714)

Main Inventor

Mark Yarvis

Brief explanation

The abstract describes a system that includes a device (referred to as the "first compute device") connected to a network. This device has interface circuitry to connect to the network and programmable circuitry to interpret a policy based on two attributes - the first attribute describes the first compute device itself, and the second attribute describes a second compute device that is connected to the first compute device via the network. The system then provides this identification information to an application on the first compute device, which causes the application to perform a specific action based on the policy.

Abstract

Systems, apparatus, articles of manufacture, and methods are disclosed. An example apparatus is a first compute device comprising: interface circuitry to connect to a network; instructions; programmable circuitry to interpret a policy based on a first attribute and a second attribute to identify an action associated with the first compute device, the first attribute to describe the first compute device, the second attribute obtained via the interface circuitry from a second compute device to describe the second compute device; and provide the identification to an application on the first compute device to cause the application to perform the action based on the policy.

METHODS AND APPARATUS TO INCREASE PRIVACY FOR FOLLOW-ME SERVICES (18343671)

Main Inventor

Akhilesh Thyagaturu

Brief explanation

The abstract describes a technology that allows for the migration of cloud-based workloads. It involves transmitting anonymous information from a user device to a network device and then migrating a virtual execution environment from one compute device to another based on the response from the network device. This virtual execution environment is responsible for executing a part of the workload for an end user device.

Abstract

Methods, apparatus, systems, and articles of manufacture to migrate cloud-based workloads are disclosed. An example instructions cause programmable circuitry to at least cause transmission of anonymized information corresponding to a user device to a network device; and cause migration of a virtual execution environment from a first compute device to a second compute device based on a response from the network device, the virtual execution environment to execute at least a portion of a workload for an end user device.

SECURE AND ATTESTABLE FUNCTIONS-AS-A-SERVICE (18216412)

Main Inventor

Ned M. Smith

Brief explanation

The abstract discusses the use of edge computing environments to bridge the gap between cloud computing and end-user devices. It introduces the concept of Functions-as-a-Service (FaaS) and how it can be used to create different flavors of services. The abstract also mentions the use of a FaaS Temporal Software-Defined Wide-Area Network (SD-WAN) to receive computing requests, break them down into FaaS flavors, create virtual networks for each flavor, execute the flavors, and return results. This approach allows for low-latency creation of virtual networks specifically designed for executing service requests.

Abstract

Software and other electronic services are increasingly being executed in cloud computing environments. Edge computing environments may be used to bridge the gap between cloud computing environments and end-user software and electronic devices, and may implement Functions-as-a-Service (FaaS). FaaS may be used to create flavors of particular services, a chain of related functions that implements all or a portion of a FaaS edge workflow or workload. A FaaS Temporal Software-Defined Wide-Area Network (SD-WAN) may be used to receive a computing request and decompose the computing request into several FaaS flavors, enable dynamic creation of SD-WANs for each FaaS flavor, execute the FaaS flavors in their respective SD-WAN, return a result, and destroy the SD-WANs. The FaaS Temporal SD-WAN expands upon current edge systems by allowing low-latency creation of SD-WAN virtual networks bound to a set of function instances that are created to a execute a particular service request.

METHODS AND APPARATUS FOR SECURED INFORMATION TRANSFER (18345865)

Main Inventor

Ned Smith

Brief explanation

The abstract describes methods and devices for secure information transfer. One example device includes programmable circuitry that can determine the characteristics of an asset owned by one entity and assign it to a carrier for transport to another entity. The first entity uses one type of decentralized security, while the second entity uses a different type. The device can obtain verified information about the asset from the carrier and transmit it to the second entity through a gateway. The second entity's gateway then receives the information for further processing.

Abstract

Methods and apparatus for secured information transfer are disclosed. An example apparatus includes programmable circuitry to execute instructions to determine characteristics of an asset associated with a first entity that utilizes a first type of decentralized security, assign the asset to a carrier for transport to a second entity that utilizes a second type of decentralized security, obtain attested information for the asset from the carrier, and transmit the attested information to the second entity via a first gateway, the first gateway to transmit the attested information for the asset to a second gateway of the second entity.

PACKET BASED IN-LINE PROCESSING FOR DATA CENTER ENVIRONMENTS (18216524)

Main Inventor

Susanne M. BALLE

Brief explanation

This abstract describes an apparatus that has a host side interface to connect to multiple CPUs that support microservice endpoints. It also has a network interface to receive packets from a network, where each packet contains multiple frames belonging to different streams and formatted using a text transfer protocol. The apparatus includes circuitry to process these frames and extract the content of a microservice functional call embedded within one of the frames. It then executes the microservice function call.

Abstract

An apparatus is described. The apparatus includes a host side interface to couple to one or more central processing units (CPUs) that support multiple microservice endpoints. The apparatus includes a network interface to receive from a network a packet having multiple frames that belong to different streams, the multiple frames formatted according to a text transfer protocol. The apparatus includes circuitry to: process the frames according to the text transfer protocol and build content of a microservice functional call embedded within a message that one of the frames transports; and, execute the microservice function call.

ENHANCED MAPPING MECHANISM FOR TRANSMISSION IDENTIFIER TO LINK IN NON-COLLOCATED ACCESS POINT MULTI-LINK DOWNLINK SYSTEMS (18341551)

Main Inventor

Laurent CARIOU

Brief explanation

This abstract describes a system for managing multiple access points (APs) that are not physically located together. The system includes a device that can identify and map traffic identifiers (TIDs) to specific links for each non-collocated AP. This mapping information is then included in beacon or probe response frames transmitted by each AP. The device can also update the mapping information in response to changes in the status of the APs and transmit the updated mapping to other APs associated with the non-collocated APs.

Abstract

This disclosure describes systems, methods, and devices related to non-collocated MLD management. A device may identify a first non-collocated access point (AP) and a second non-collocated AP associated with a non-collocated AP multi-link device (MLD). The device may determine traffic identifier (TID)-to-link mapping for the first non-collocated AP and second non-collocated AP. The device may include the TID-to-link mapping element in beacon or probe response frames transmitted by each of the first non-collocated AP and second non-collocated AP. The device may update the TID-to-link mapping element in response to changes in status of either the first non-collocated AP or the second non-collocated AP. The device may transmit the updated TID-to-link mapping element to other APs affiliated with the non-collocated AP MLD.

RELEASE-18 (REL-18) SUPPORT OF TWO TIMING ADVANCES (TAS) FOR SINGLE CELL (18307484)

Main Inventor

Xun Tang

Brief explanation

The abstract describes a technology that allows a user equipment (UE) in a cellular network to support two timing advances (TAs) in a single cell. TAs are used to synchronize the timing between the UE and the base station. The abstract mentions that the base station can indicate the TAs to the UE through certain messages. The abstract also mentions that there may be other embodiments of this technology.

Abstract

Systems, apparatuses, methods, and computer-readable media are provided for a user equipment (UE) in a new radio (NR) system to support two timing advances (TAs) in a single cell of a cellular network. In some embodiments, one or more of the TAs may be indicated to the UE by a base station (e.g., in a MAC RAR or a MAC CE). Other embodiments may be described and/or claimed.

MICROELECTRONIC ASSEMBLIES HAVING CONDUCTIVE STRUCTURES WITH DIFFERENT THICKNESSES (18344944)

Main Inventor

Brandon C. Marin

Brief explanation

The abstract describes microelectronic assemblies and their components. These assemblies include a substrate with a dielectric layer that contains an electroless catalyst, such as palladium, gold, silver, ruthenium, cobalt, copper, nickel, titanium, aluminum, lead, silicon, or tantalum. The dielectric layer also contains two conductive traces with different thicknesses. The first trace has a thickness between 4 um and 143 um, while the second trace has a thickness between 2 um and 141 um. The first trace is thicker than the second trace, and both traces have sloped sidewalls.

Abstract

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a dielectric layer, in a substrate, the dielectric layer including an electroless catalyst, wherein the electroless catalyst includes one or more of palladium, gold, silver, ruthenium, cobalt, copper, nickel, titanium, aluminum, lead, silicon, and tantalum; a first conductive trace having a first thickness in the dielectric layer, wherein the first thickness is between 4 um and 143 um; and a second conductive trace having a second thickness in the dielectric layer, wherein the second thickness is between 2 um and 141 um, wherein the first thickness is greater than the second thickness, and wherein the first conductive trace and the second conductive trace have sloped sidewalls.

COMPACT REAR MOUNTED HEAT EXCHANGERS AND RELATED METHODS (18344620)

Main Inventor

Shaorong Zhou

Brief explanation

The abstract describes compact heat exchangers that can be mounted at the rear of a server chassis. These heat exchangers have an inlet and outlet for airflow and are held in place by a holder frame and bracket.

Abstract

Compact rear mounted modular heat exchangers and related methods are disclosed herein. An example apparatus disclosed herein includes a heat exchanger having an air flow inlet and an air flow outlet, a holder frame to receive a component of a server chassis, and a bracket coupled to the holder frame, the bracket to retain the heat exchanger adjacent a rear of the server chassis.