US Patent Application 18216989. SIZE AND EFFICIENCY OF DIES simplified abstract

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SIZE AND EFFICIENCY OF DIES

Organization Name

Intel Corporation


Inventor(s)

Mathew J. Manusharow of Phoenix AZ (US)


Jonathan Rosenfeld of Portland OR (US)


SIZE AND EFFICIENCY OF DIES - A simplified explanation of the abstract

  • This abstract for appeared for US patent application number 18216989 Titled 'SIZE AND EFFICIENCY OF DIES'

Simplified Explanation

The abstract describes an integrated circuit package that includes two integrated circuit dies connected to an organic substrate. The package also includes a multi-die interconnect bridge embedded within the substrate and a termination resistor located within this bridge. The termination resistor is associated with a circuit in one of the integrated circuit dies.


Original Abstract Submitted

An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.