US Patent Application 17728256. SELF-RESETTING CLOCK GENERATOR simplified abstract
Contents
SELF-RESETTING CLOCK GENERATOR
Organization Name
Inventor(s)
Gururaj Shamanna of Austin TX (US)
Naveen Kumar of Bangalore (IN)
Jagadeesh Chandra Salaka of BENGALURU (IN)
Pascal A. Meinerzhagen of Hillsboro OR (US)
SELF-RESETTING CLOCK GENERATOR - A simplified explanation of the abstract
- This abstract for appeared for US patent application number 17728256 Titled 'SELF-RESETTING CLOCK GENERATOR'
Simplified Explanation
The abstract describes a new clock generator circuit that improves its operation. The circuit includes a clock gate that generates a stable positive clock signal based on various input signals. It also includes two banks of transistors that control the assertion and de-assertion of a clock signal. Additionally, there is a reset circuit that generates a reset signal based on other clock signals. Overall, this new circuit aims to enhance the performance of clock generation in electronic systems.
Original Abstract Submitted
An apparatus, system, and method for improved clock generator circuit operation. A self-resetting clock generator circuit includes a keeper-free clock gate configured to generate a stabilized positive clock (PCLK) signal based on an enable (ENBL) signal, a positive clock (PCLK), a reset (RST) signal, and an external clock (SOC CLK), a first bank of transistors configured to assert a clock signal (ST CLK) based on PCLK, a second bank of transistors in parallel with the first bank of transistors and configured to de-assert (1->0) ST CLK # based on PCLK assertion (0->1), and a logic gate-based reset circuit configured to generate the RST signal based on the SOC CLK and the ST CLK #.
