US Patent Application 17728147. PACKAGING ARCHITECTURE FOR WAFER-SCALE KNOWN-GOOD-DIE TO KNOWN-GOOD-DIE HYBRID BONDING simplified abstract
PACKAGING ARCHITECTURE FOR WAFER-SCALE KNOWN-GOOD-DIE TO KNOWN-GOOD-DIE HYBRID BONDING
Organization Name
Inventor(s)
Omkar G. Karhade of Chandler AZ (US)
Nitin A. Deshpande of Chandler AZ (US)
Debendra Mallik of Chandler AZ (US)
Babak Sabi of Portland OR (US)
PACKAGING ARCHITECTURE FOR WAFER-SCALE KNOWN-GOOD-DIE TO KNOWN-GOOD-DIE HYBRID BONDING - A simplified explanation of the abstract
- This abstract for appeared for US patent application number 17728147 Titled 'PACKAGING ARCHITECTURE FOR WAFER-SCALE KNOWN-GOOD-DIE TO KNOWN-GOOD-DIE HYBRID BONDING'
Simplified Explanation
The abstract describes a microelectronic assembly that consists of multiple layers connected by fusion bonds. The assembly includes a package substrate attached to the first layer, which contains one or more dies (small chips). The second layer in the stack also contains one or more dies and is connected to the first layer. Between the adjacent surfaces of the dies in either layer, there is a copper lining that covers and contacts these surfaces. The dies can be either dummy dies (without any functioning circuits) or integrated circuit (IC) dies with functional circuits.
Original Abstract Submitted
Embodiments of a microelectronic assembly comprise a microelectronic assembly, comprising: a stack of layers coupled by at least fusion bonds; a package substrate coupled to a first layer in the stack of layers; one or more dies in the first layer; and one or more dies in a second layer in the stack of layers, the second layer coupled to the first layer, wherein: a copper lining is between adjacent surfaces of any two adjacent dies in at least one of the first layer and the second layer, and the copper lining contacts and substantially covers the adjacent surfaces. In various embodiments, the dies comprise dummy dies and integrated circuit (IC) dies, the dummy dies are one of: semiconductor dies without any ICs, and semiconductor dies having non-functional ICs, and the IC dies comprise semiconductor dies having functional ICs.
