US Patent Application 18345497. METHODS AND APPARATUS FOR A REMOTE PROCESSING ACCELERATION ENGINE simplified abstract

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METHODS AND APPARATUS FOR A REMOTE PROCESSING ACCELERATION ENGINE

Organization Name

Intel Corporation


Inventor(s)

Thomas E. Willis of Redwood City CA (US)


Vered Bar Bracha of Somerville MA (US)


Dinesh Kumar of Portland OR (US)


David Anderson of Hillsboro OR (US)


Dror Bohrer of Kiryat Tiv'on (IL)


Stephen Ibanez of Escondido CA (US)


Salma Johnson of Littleton MA (US)


Brad Burres of Waltham MA (US)


METHODS AND APPARATUS FOR A REMOTE PROCESSING ACCELERATION ENGINE - A simplified explanation of the abstract

  • This abstract for appeared for US patent application number 18345497 Titled 'METHODS AND APPARATUS FOR A REMOTE PROCESSING ACCELERATION ENGINE'

Simplified Explanation

The abstract describes a remote processing acceleration engine that includes an infrastructure processing unit (IPU). The IPU has various components such as an offload engine driver, network interface circuitry, and RPC offload circuitry. The offload engine driver allows access to a remote procedure call (RPC) from business logic circuitry. The RPC offload circuitry selects a destination based on its ability to perform the operation using remote direct memory access (RDMA). The network interface circuitry is used to communicate the operation to the selected destination.


Original Abstract Submitted

Systems, apparatus, articles of manufacture, and methods are disclosed for a remote processing acceleration engine. Disclosed is an infrastructure processing unit (IPU) comprising an offload engine driver to access a remote procedure call (RPC) from business logic circuitry, network interface circuitry, and RPC offload circuitry to select a destination to perform an operation associated with the RPC call, the destination selected based on an ability of the destination to perform the operation using remote direct memory access (RDMA), and cause communication of the operation to the destination via the network interface circuitry.