US Patent Application 18216984. MID-PROCESSING REMOVAL OF SEMICONDUCTOR FINS DURING FABRICATION OF INTEGRATED CIRCUIT STRUCTURES simplified abstract
Contents
MID-PROCESSING REMOVAL OF SEMICONDUCTOR FINS DURING FABRICATION OF INTEGRATED CIRCUIT STRUCTURES
Organization Name
Inventor(s)
Mehmet O. Baykan of Beaverton OR (US)
Anurag Jain of Portland OR (US)
Szuya S. Liao of Portland OR (US)
MID-PROCESSING REMOVAL OF SEMICONDUCTOR FINS DURING FABRICATION OF INTEGRATED CIRCUIT STRUCTURES - A simplified explanation of the abstract
- This abstract for appeared for US patent application number 18216984 Titled 'MID-PROCESSING REMOVAL OF SEMICONDUCTOR FINS DURING FABRICATION OF INTEGRATED CIRCUIT STRUCTURES'
Simplified Explanation
This abstract describes techniques for creating integrated circuit structures with multiple semiconductor fins, which can be used to create non-planar transistor structures. The techniques involve removing partially-formed fins during the manufacturing process to ensure that the dimensions of the fins are uniform. This is achieved by using a selective etch stop built into the semiconductor structure to partially form the fins, and then removing some of the fins using sacrificial fin cut mask layer(s). After the removal, the process continues by etching trenches between the remaining partially-formed fins to create the transistor channel portion of the fins. A liner material may be added to protect the partially-formed fins during this deep trench etching process.
Original Abstract Submitted
Techniques are disclosed for forming integrated circuit structures having a plurality of semiconductor fins, which in turn can be used to form non-planar transistor structures. The techniques include a mid-process removal of one or more partially-formed fins. The resulting integrated circuit structure includes a plurality of semiconductor fins having relatively uniform dimensions (e.g., fin width and trough depth). In an embodiment, the fin forming procedure includes partially forming a plurality of fins, using a selective etch stop built into the semiconductor structure in which the fins are being formed. One or more of the partially-formed fins are removed via sacrificial fin cut mask layer(s). After fin removal, the process continues by further etching trenches between the partially-formed fins (deep etch) to form portion of fins that will ultimately include transistor channel portion. A liner material may be deposited to protect the partially-formed fins during this subsequent deep trench etch.
