US Patent Application 18216275. TECHNIQUES FOR DIE TILING simplified abstract
Contents
TECHNIQUES FOR DIE TILING
Organization Name
Inventor(s)
Srinivas Pietambaram of Chandler AZ (US)
Deepak Kulkarni of Chandler AZ (US)
TECHNIQUES FOR DIE TILING - A simplified explanation of the abstract
- This abstract for appeared for US patent application number 18216275 Titled 'TECHNIQUES FOR DIE TILING'
Simplified Explanation
This abstract describes techniques for creating fine node heterogeneous-chip packages. The method involves connecting the electrical terminals of two base dies using a silicon bridge, and then forming an organic substrate around the bridge and adjacent to the base dies. Finally, a fine node die is connected to the second side of one of the base dies.
Original Abstract Submitted
Techniques are provided for fine node heterogeneous-chip packages. In an example, a method of making a heterogeneous-chip package can include coupling electrical terminals of a first side of a first base die to electrical terminals of a first side of a second base die using a silicon bridge, forming an organic substrate about the silicon bridge and adjacent the first sides of the first and second base dies, and coupling a fine node die to a second side of at least one of the first base die or the second base die.
