CHANGXIN MEMORY TECHNOLOGIES, INC. patent applications published on November 30th, 2023

Summary of the patent applications from CHANGXIN MEMORY TECHNOLOGIES, INC. on November 30th, 2023

CHANGXIN MEMORY TECHNOLOGIES, INC. has recently filed several patents related to semiconductor structures and manufacturing methods. These patents aim to improve the performance, functionality, and capacity of memory devices.

Summary: - The patents describe various semiconductor structures consisting of bonded layers, redistribution lines, word lines, bit lines, and isolation layers. - The manufacturing methods involve forming active areas, word line structures, bit line structures, and capacitor structures on substrates. - The designs focus on optimizing the contact between different layers, improving the storage capacity of capacitances, and enhancing production efficiency. - Notable applications include memory cell arrays, control chips, storage chips, and transistor designs with metal oxide semiconductor layers.

Bullet points:

• CHANGXIN MEMORY TECHNOLOGIES, INC. has filed recent patents related to semiconductor structures and manufacturing methods.
• The patents aim to improve the performance, functionality, and capacity of memory devices.
• The designs involve bonded layers, redistribution lines, word lines, bit lines, and isolation layers.
• The manufacturing methods include forming active areas, word line structures, bit line structures, and capacitor structures on substrates.
• The patents focus on optimizing contact between layers, increasing storage capacity, and enhancing production efficiency.
• Applications include memory cell arrays, control chips, storage chips, and transistor designs with metal oxide semiconductor layers.

Notable applications:

• Memory cell arrays with optimized word lines and bit lines.
• Transistor designs utilizing metal oxide semiconductor layers in the channel layer.
• Capacitor structures with increased storage capacity and improved production efficiency.

Patent applications for CHANGXIN MEMORY TECHNOLOGIES, INC. on November 30th, 2023

PACKAGE SUBSTRATE, APPARATUS FOR TESTING POWER SUPPLY NOISE AND METHOD FOR TESTING POWER SUPPLY NOISE (17951625)

Main Inventor

Honglong SHI

Brief explanation

The patent application describes a package substrate, apparatus, and method for testing power supply noise.

• The package substrate has multiple pad arrays, each containing power supply pads.
• Power supply pads of the same type in the multiple pad arrays are divided into a test pad and a power supply pad set.
• The power supply pad set includes all power supply pads, except the test pad, of the same type, and they are electrically connected together.
• The test pad is used to perform noise testing of at least one internal power supply in a chip to be tested.
• The invention simplifies the testing process for power supply noise by grouping power supply pads and providing a dedicated test pad.

Abstract

A package substrate, an apparatus for testing power supply noise, and a method for testing power supply noise are provided. The package substrate includes multiple pad arrays, and each of the multiple pad arrays at least includes power supply pads. Power supply pads belonging to a same power supply type in the multiple pad arrays are divided into a test pad and a power supply pad set. The power supply pad set includes power supply pads, other than the test pad, among the power supply pads belonging to the same power supply type, all the power supply pads in the power supply pad set are electrically connected together, and the test pad is configured to perform noise testing of at least one internal power supply corresponding to the same power supply type in a chip to be tested.

METHOD AND DEVICE FOR EVALUATING PERFORMANCE OF SEQUENTIAL LOGIC ELEMENT (17872479)

Main Inventor

Zengquan WU

Brief explanation

- The patent application describes a method for evaluating the performance of a sequential logic element.

- The method involves inputting a clock signal and a data signal to the sequential logic element to be tested. - The setup time of the sequential logic element is decremented from a first preset value to a second preset value based on a preset decrement step. - The first preset value is determined by the setup time when the sequential logic element outputs a target sampled value. - The second preset value is determined by the setup time when the sequential logic element outputs a reverse value of the target sampled value. - An evaluation parameter of the sequential logic element is determined based on the sampled value output by the sequential logic element after each decrement of the setup time. - The performance of the sequential logic element is evaluated based on the evaluation parameter.

Abstract

A method for evaluating performance of a sequential logic element includes: inputting a preset clock signal and a data signal to a sequential logic element to be tested; decrementing a setup time of the sequential logic element from a first preset value to a second preset value based on a preset decrement step, where the first preset value is determined by a setup time when the sequential logic element to be tested outputs a target sampled value, and the second preset value is determined by a setup time when the sequential logic element outputs a reverse value of the target sampled value; and determining an evaluation parameter of the sequential logic element based on a sampled value output by the sequential logic element after each decrement of the setup time, and evaluating performance of the sequential logic element based on the evaluation parameter of the sequential logic element to be tested.

DATA PROCESSING CIRCUITRY AND METHOD, AND SEMICONDUCTOR MEMORY (18448891)

Main Inventor

Yinchuan GU

Brief explanation

The patent application describes a data processing circuitry that includes a preprocessing circuit and a drive circuit.

• The preprocessing circuit receives an initial data signal and generates a data signal to be processed and an auxiliary data signal based on the initial data signal.
• The drive circuit is connected to the preprocessing circuit and performs several adjustments to generate a target data signal.
• The drive circuit adjusts an initial calibration code based on a preset scenario to obtain a target calibration code.
• The drive circuit also adjusts the value of a drive resistance based on the target calibration code.
• Additionally, the drive circuit adjusts the drive capability of the data signal to be processed based on the auxiliary data signal and the adjusted drive resistance.
• The result is the generation of a target data signal with improved accuracy and performance.

Abstract

A data processing circuitry includes: a preprocessing circuit, configured to receive an initial data signal and generate a data signal to be processed and an auxiliary data signal according to the initial data signal; and a drive circuit, connected with the preprocessing circuit and configured to: adjust an initial calibration code according to a preset scenario, to obtain a target calibration code; adjust a value of a drive resistance of the drive circuit according to the target calibration code; and adjust a drive capability of the data signal to be processed according to the auxiliary data signal and the adjusted drive resistance, to generate a target data signal.

METHOD AND APPARATUS FOR TESTING COMMAND, TEST PLATFORM, AND READABLE STORAGE MEDIUM (17899056)

Main Inventor

Yu LI

Brief explanation

The patent application describes a method and apparatus for testing a command.

• The method involves determining the duration of a deselect command based on the time interval between a target command and historical commands.
• The target command is then sent to a memory after the deselect command.
• The purpose of this invention is to improve the testing process for commands sent to a memory.

Abstract

A method and apparatus for testing a command are provided. The method includes that: when the test platform exists a target command to be sent to a memory, a duration of a deselect command is determined according to a minimum time interval between a target command and each of historical commands and the time when the each of the historical commands is sent and the present time; the target command is sent to the memory after the deselect command.

METHOD AND APPARATUS FOR CHECKING SIGNAL LINE (17898727)

Main Inventor

Min MIN

Brief explanation

- The patent application describes a method and apparatus for checking a signal line in a circuit layout.

- The method involves obtaining custom design information for a specific signal line in a circuit schematic. - Based on this information, a layout design rule is generated for the target signal line. - The circuit layout corresponding to the circuit schematic is then checked to see if the target signal line meets the layout design rule. - If the target signal line does not meet the layout design rule, a first label is added to indicate this. - The purpose of the first label is to identify that the target signal line does not comply with the layout design rule.

Abstract

A method and an apparatus for checking a signal line are provided. The method includes: obtaining custom design information of a target signal line in a circuit schematic, and generating a layout design rule corresponding to the target signal line based on the custom design information; checking whether the target signal line meets the layout design rule in a circuit layout corresponding to the circuit schematic; and adding a first label to a position of the target signal line in the circuit layout when the target signal line in the circuit layout does not meet the layout design rule. The first label is configured to indicate that the target signal line does not meet the layout design rule.

TIMING SEQUENCE CONTROL CIRCUIT, TIMING SEQUENCE CONTROL METHOD, AND SEMICONDUCTOR MEMORY (18169159)

Main Inventor

Kangling JI

Brief explanation

The patent application describes a timing sequence control circuit that includes a signal transmission module and a timing sequence compensation module.

• The signal transmission module receives an initial sampling signal and generates a sampling signal.
• The timing sequence compensation module includes a compensation capacitor and is connected to the signal transmission module.
• The timing sequence compensation module receives an adjustable supply voltage and adjusts the compensation delay of the initial sampling signal based on the supply voltage and the compensation capacitor.
• The purpose of the compensation delay adjustment is to ensure that the time difference between the sampling signal and the to-be-sampled Data (DQ) signal meets a preset requirement.

Abstract

A timing sequence control circuit includes: a signal transmission module and a timing sequence compensation module, and the timing sequence compensation module is connected with the signal transmission module. Herein, the signal transmission module is configured to receive an initial sampling signal and transmit the initial sampling signal to generate a sampling signal. The timing sequence compensation module at least includes a compensation capacitor and is configured to receive an adjustable supply voltage, and perform compensation delay adjustment on the initial sampling signal according to the supply voltage and the compensation capacitor, so that the time difference between the sampling signal and a to-be-sampled Data (DQ) signal meets a preset requirement.

REFRESH ADDRESS GENERATION CIRCUIT AND METHOD, MEMORY, AND ELECTRONIC DEVICE (18332706)

Main Inventor

Yinchuan GU

Brief explanation

The patent application describes a refresh address generation circuit.

• The circuit includes a refresh control circuit that receives refresh commands and performs refresh operations.
• The refresh control circuit outputs a first clock signal when the number of refresh operations is below a preset value, and a second clock signal when the number of refresh operations is equal to the preset value.
• An address generator is coupled to the refresh control circuit and stores a first address.
• The address generator outputs a to-be-refreshed address in response to the first clock signal during each refresh operation.
• The to-be-refreshed address includes the first address, and the first address is changed in response to the second clock signal.

Abstract

A refresh address generation circuit includes: a refresh control circuit configured to sequentially receive first refresh commands and perform first refresh operations respectively, output a first clock signal when the number of the first refresh operations is less than a preset value or output a second clock signal when the number of the first refresh operations is equal to the preset value n, where n is a positive integer greater than or equal to 1; an address generator coupled to refresh control circuit, pre-storing a first address, receiving the first clock signal or the second clock signal, outputting a first to-be-refreshed address in response to the first clock signal during each first refresh operation, the first to-be-refreshed address includes the first address, and changing the first address in response to the second clock signal.

REFRESH ADDRESS GENERATION CIRCUIT (18153312)

Main Inventor

Yinchuan GU

Brief explanation

The patent application describes a circuit for generating refresh addresses.

• The circuit includes a refresh control circuit and an address generator.
• The refresh control circuit receives multiple refresh commands and performs corresponding refresh operations.
• It outputs a first clock signal when the number of refresh operations is less than m, and a second clock signal when the number of refresh operations is equal to m.
• The address generator is connected to the refresh control circuit and stores a first address.
• It receives the first or second clock signal and outputs an address to be refreshed during each refresh operation.
• The first address is changed in response to the second clock signal.
• The address to be refreshed includes the first address and a second address with the lowest bit opposite to that of the first address.

Abstract

A refresh address generation circuit includes: a refresh control circuit and an address generator. The refresh control circuit receives multiple first refresh commands in sequence and performs multiple first refresh operations accordingly, outputs a first clock signal when the number of first refresh operations is less than m, and outputs a second clock signal when the number of first refresh operation is equal to m. The address generator is coupled to the refresh control circuit, and configured to prestore a first address and receive the first clock signal or the second clock signal, and during each first refresh operation, output an address to be refreshed in response to the first clock signal and change the first address in response to the second clock signal. The address to be refreshed includes a first address and a second address with the lowest bit opposite to that of the first address.

REFRESH CONTROL CIRCUIT, MEMORY, AND REFRESH CONTROL METHOD (18157558)

Main Inventor

Liang ZHANG

Brief explanation

The patent application describes a refresh control circuit that includes three main components: a processing circuit, a logic circuit, and a power supply circuit.

• The processing circuit receives a refresh command signal and performs pulse combination processing on it. The refresh command signal has a series of pulses in a first time period and maintains a constant level state in a second time period. These two time periods alternate.

• The logic circuit receives the refresh command signal and the refresh combined signal from the processing circuit. It performs logical operation processing on these signals to obtain a target control signal.

• The power supply circuit receives the target control signal and determines whether to perform a power supply operation based on the level state of the target control signal.

Abstract

A refresh control circuit includes: a processing circuit, configured to receive a refresh command signal, and perform pulse combination processing on the refresh command signal to obtain a refresh combined signal, the refresh command signal having a plurality of pulses in a first time period and keeping a level state unchanged in a second time period, and the first time period and the second time period existing alternately; a logic circuit, configured to receive the refresh command signal and the refresh combined signal, and perform logical operation processing on the refresh command signal and the refresh combined signal to obtain a target control signal; and a power supply circuit, configured to receive the target control signal, and determine whether to perform a power supply operation according to the level state of the target control signal.

SIGNAL SAMPLING CIRCUIT AND SEMICONDUCTOR MEMORY (18449060)

Main Inventor

Zequn HUANG

Brief explanation

The patent application describes a signal sampling circuit and a semiconductor memory.

• The signal sampling circuit samples a first CS signal and a first CA signal to obtain a second CS signal and a second CA signal.
• A logical operation circuit performs a logical operation on the first clock signal and the second CS signal.
• A command decoding circuit decodes and samples an initial command signal based on the second CS signal and the CS clock signal.
• An output combined circuit samples the second odd CA signal and the second even CA signal based on the even CS clock signal and the odd CS clock signal.
• The output combined circuit also samples the second odd CA signal and the second even CA signal based on the odd CS clock signal and the even CS clock signal.

Abstract

A signal sampling circuit and a semiconductor memory are provided. The signal sampling circuit includes: an input sampling circuit, configured to sample a first CS signal and a first CA signal according to a first clock signal to obtain a second CS signal and a second CA signal; a logical operation circuit, configured to perform a logical operation on the first clock signal and the second CS signal; a command decoding circuit, configured to decode and sample an initial command signal according to the second CS signal and the CS clock signal; and an output combined circuit, configured to: sample the second odd CA signal and the second even CA signal according to the even CS clock signal and the odd CS clock signal; and sample the second odd CA signal and the second even CA signal according to the odd CS clock signal and the even CS clock signal.

POWER SUPPLY SWITCHING CIRCUIT AND MEMORY (18327062)

Main Inventor

Yupeng FAN

Brief explanation

The patent application describes a power supply switching circuit that reduces the time required to turn on or off different output subcircuits simultaneously. This improves the efficiency and reliability of the device.

• The power supply switching circuit generates control signals using input signals and drive signals that are opposite in phase.
• By utilizing these control signals, the circuit reduces or eliminates the overlap time needed to turn on or off different output subcircuits.
• This allows for more effective output from the device and improves its reliability.
• Compared to other methods of eliminating overlap time, such as delay, the power supply switching circuit is simpler and more reliable in control logic.
• The circuit is also less sensitive to process variations, further enhancing the device's reliability.

Abstract

Embodiments provide a power supply switching circuit, which generates a first control signal jointly by utilizing a first input signal and a first drive signal opposite in phase to a second control signal, and generates the second control signal jointly by utilizing a second input signal and a second drive signal opposite in phase to the first control signal, such that time (i.e., overlap time) required for simultaneously turning on or off a first output subcircuit and a second output subcircuit is greatly reduced or even eliminated, effective output of an output node is implemented, and reliability of a device is improved. Furthermore, compared with eliminating the overlap time by means of delay, eliminating the overlap time by means of the power supply switching circuit is simple and reliable in control logic and is insensitive to process, which further improves the reliability of the device.

SIGNAL SAMPLING CIRCUIT AND SEMICONDUCTOR MEMORY (18448897)

Main Inventor

Zequn HUANG

Brief explanation

The patent application describes a signal sampling circuit that includes several components to process command signals and chip select signals. 

• The signal input circuit determines the command signal and chip select signal to be processed.
• The clock processing circuit performs two-stage sampling and logical operations on the chip select signal to obtain a chip select clock signal.
• The chip select control circuit samples the chip select signal to obtain an intermediate chip select signal and performs logical operations on it, along with the command signal, to obtain a command decoding signal.
• The output sampling circuit samples the command decoding signal according to the chip select clock signal to obtain a target command signal.

The innovation in this patent application lies in the design and configuration of the signal sampling circuit, which allows for efficient processing and decoding of command signals based on chip select signals.

Abstract

A signal sampling circuit includes: a signal input circuit, configured to determine a to-be-processed command signal and a to-be-processed chip select signal; a clock processing circuit, configured to perform two-stage sampling and logical operation on the to-be-processed chip select signal according to a first clock signal to obtain a chip select clock signal; a chip select control circuit, configured to perform sampling on the to-be-processed chip select signal according to the first clock signal to obtain an intermediate chip select signal, and perform logical operations on the intermediate chip select signal, the to-be-processed chip select signal and the to-be-processed command signal to obtain a command decoding signal; and an output sampling circuit, configured to perform sampling on the command decoding signal according to the chip select clock signal to obtain a target command signal.

METHOD FOR SENSE MARGIN DETECTION FOR SENSE AMPLIFIER AND ELECTRONIC DEVICE (17868774)

Main Inventor

Xikun CHU

Brief explanation

- The patent application describes a method for detecting sense margin for a sense amplifier and an electronic device.

- The method involves writing data to memory cells connected to a bit line and word lines, and performing a reverse write operation on the memory cells. - Write operations are then performed on memory cells connected to a second bit line. - The second memory cell is read, and the preset row precharge time is determined as the margin value of row precharge time for the first sense amplifier when the first data is not correctly read.

Abstract

Embodiments provide a method for sense margin detection for a sense amplifier and an electronic device. The method includes: writing first data and second data respectively to a first memory cell and a second memory cell connected to a first bit line, the first memory cell and the second memory cell being respectively connected to a first word line and a second word line adjacent to each other, and the first bit line being connected to a first sense amplifier; performing a reverse write operation on the first memory cell and the second memory cell; performing write operations on memory cells connected to the second bit line; and reading the second memory cell, and determining the preset row precharge time to be a margin value of row precharge time of the first sense amplifier when the first data is not correctly read.

ANTI-FUSE STRUCTURE, ANTI-FUSE ARRAY AND MEMORY (17929747)

Main Inventor

Chuangming HOU

Brief explanation

The patent application describes an anti-fuse structure with two units, each consisting of a selection transistor and multiple anti-fuse cells.

• The first unit includes a first selection transistor, a first anti-fuse cell, and a second anti-fuse cell.
• The second unit includes a second selection transistor, a third anti-fuse cell, and a fourth anti-fuse cell.
• Both units share an active region with independent extension parts on opposite sides.
• The first and second extension parts are on one side, while the third and fourth extension parts are on the other side.
• The first anti-fuse cell is located at the first extension part, the second anti-fuse cell at the second extension part, the third anti-fuse cell at the third extension part, and the fourth anti-fuse cell at the fourth extension part.

Abstract

An anti-fuse structure includes: a first unit including a first selection transistor, a first anti-fuse (AF) cell and a second AF cell; and a second unit including a second selection transistor, a third AF cell and a fourth AF cell. The first unit and second unit share an active region, which is provided with a first extension part and a second extension part which are independent of each other at a first side, and provided with a third extension part and a fourth extension part which are independent of each other at a second side, the first side being opposite to the second side. The first AF cell is arranged at the first extension part, the second AF cell is arranged at the second extension part, the third AF cell is arranged at the third extension part, and the fourth AF cell is arranged at the fourth extension part.

CIRCUIT FOR CALIBRATION CONTROL, ELECTRONIC DEVICE AND METHOD FOR CALIBRATION CONTROL (18448340)

Main Inventor

Kai TIAN

Brief explanation

The abstract describes a circuit for calibration control that includes an off-chip calibration circuit and a mode switching circuit. The off-chip calibration circuit consists of a preprocessing circuit and a mapping circuit.

• The preprocessing circuit receives a current set of environmental parameters and decodes them to generate parameter decoding signals.
• The mapping circuit takes the parameter decoding signals as input and generates a first calibration code based on these signals.
• The mode switching circuit receives a calibration mode signal and the first calibration code.
• If the calibration mode signal indicates an off-chip calibration mode, the mode switching circuit determines the first calibration code as a ZQ calibration code.

Abstract

A circuit for calibration control includes an off-chip calibration circuit and a mode switching circuit, and the off-chip calibration circuit includes a preprocessing circuit and a mapping circuit. The preprocessing circuit is configured to receive a current set of environmental parameters, decode the current set of environmental parameters and output parameter decoding signals. The mapping circuit is configured to receive the parameter decoding signals and output a first calibration code according to the parameter decoding signals. The mode switching circuit is configured to receive a calibration mode signal and the first calibration code, and determine the first calibration code as a ZQ calibration code in a case where the calibration mode signal indicates an off-chip calibration mode.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF (17815623)

Main Inventor

Yi TANG

Brief explanation

The patent application describes a semiconductor structure and a method for manufacturing it.

• The method involves providing a substrate with different regions.
• A first stacked structure is formed on the substrate, consisting of a sacrificial layer and a semiconductor layer.
• A second stacked structure is formed on top of the first stacked structure, also consisting of a sacrificial layer and a semiconductor layer.
• An ion implantation process is performed on the semiconductor layers of both stacked structures.
• The purpose of the invention is to provide a simplified and efficient method for manufacturing a semiconductor structure.

Abstract

Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The method includes: providing a substrate, wherein the substrate includes a word line region, a bit line region, and a capacitive region arranged adjacently; forming a first stacked structure that covers a surface of the substrate, wherein the first stacked structure includes a first sacrificial layer located on the surface of the substrate and a first semiconductor layer located on a surface of the first sacrificial layer; forming a second stacked structure that covers a surface of the first stacked structure, wherein the second stacked structure includes a second sacrificial layer located on the surface of the first stacked structure and a second semiconductor layer located on a surface of the second sacrificial layer; and performing an ion implantation on the first semiconductor layer and the second semiconductor layer.

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SEMICONDUCTOR STRUCTURE (18167024)

Main Inventor

Peimeng WANG

Brief explanation

The patent application describes a method for forming a semiconductor structure using various layers on a substrate.

• The layers include an insulation layer, initial metal conductive layer, initial sacrifice layer, and a mask layer.
• A metal conductive layer and sacrifice layer are formed by etching the initial layers based on a patterned mask layer.
• The patterned mask layer is removed using an ashing process.
• The sacrifice layer and by-products are removed, exposing the metal conductive layer, through a corrosion process using an alkaline corrosion solution.
• An isolation structure is formed between adjacent metal conductive layers.

Abstract

A semiconductor structure is formed by: providing a substrate, wherein an insulation layer, an initial metal conductive layer, an initial sacrifice layer, and a mask layer stacking in sequence are formed on the substrate, wherein the initial sacrifice layer includes a metal oxide layer; forming a metal conductive layer and a sacrifice layer atop the metal conductive layer by etching the initial sacrifice layer and the initial metal conductive layer using an oxygen source gas as an etching gas based on a patterned mask layer; removing the patterned mask layer by performing an ashing process using the oxygen source gas as the etching gas; removing the sacrifice layer as well as a by-product formed during the etching and the ashing process and exposing the metal conductive layer by performing a corrosion process using an alkaline corrosion solution; and forming an isolation structure between adjacent metal conductive layers.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF (17887775)

Main Inventor

Yongxiang LI

Brief explanation

The patent application describes a semiconductor structure and a method for manufacturing it.

• The method involves providing a substrate and creating an ion implantation area within the substrate.
• An initial word line trench is formed in the substrate, extending from the surface into the ion implantation area.
• The initial trench is then widened to create a word line trench, with the bottom of the trench being wider than the minimum width required.
• The purpose of widening the trench is not specified in the abstract.

Abstract

A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method includes: providing a substrate; forming an ion implantation area in the substrate, an upper surface of the ion implantation area having a distance from an upper surface of the substrate; forming an initial word line trench in the substrate, the initial word line trench extending from the upper surface of the substrate into the ion implantation area; widening the initial word line trench to form a word line trench, a width of a bottom of the word line trench being greater than a minimum width of the word line trench.

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SEMICONDUCTOR STRUCTURE (18163135)

Main Inventor

YOUMING LIU

Brief explanation

The patent application describes a semiconductor structure and a method for forming it.

• The structure includes a substrate, a switching transistor, and a storage transistor.
• The switching transistor has a first gate electrode, a first channel layer, and first and second source-drain electrodes.
• The storage transistor has a second gate electrode, a second channel layer, and third and fourth source-drain electrodes.
• The second gate electrode is electrically connected to the second source-drain electrode.
• The storage transistor is designed to store charge.

Abstract

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a switching transistor and a storage transistor. The switching transistor includes a first gate electrode, a first channel layer coating a portion of the first gate electrode, and a first source-drain electrode and a second source-drain electrode both covering a surface of the first channel layer. The storage transistor includes a second gate electrode, a second channel layer coating a portion of the second gate electrode, and a third source-drain electrode and a fourth source-drain electrode both covering a surface of the second channel layer. A portion of the second gate electrode extending out of the second channel layer in a first direction is electrically connected to the second source-drain electrode. The storage transistor is configured to store charge.

SEMICONDUCTOR STRUCTURE AND FORMATION METHOD THEREOF (17878046)

Main Inventor

Xiaojie LI

Brief explanation

The patent application describes a semiconductor structure and a method for forming it.

• The semiconductor structure includes a stacked layer on a substrate, with multiple semiconductor layers spaced along a first direction.
• The stacked layer has a transistor region, a capacitor region, and a bit line region.
• A capacitor is formed in the capacitor region, extending along a second direction.
• A word line is formed in the transistor region, extending along the first direction.
• A bit line is formed in the bit line region, extending along the third direction.

Abstract

Embodiments relates to a semiconductor structure and a formation method thereof. The method for forming a semiconductor structure includes: forming a stacked layer on a top surface of a substrate, where the stacked layer includes a plurality of semiconductor layers spaced along a first direction, the stacked layer includes a transistor region, and a capacitor region and a bit line region; forming a capacitor extending along the second direction in the capacitor region; forming a word line in the transistor region, the word line extending along the first direction; and forming a bit line in the bit line region, the bit line extending along the third direction.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF (18150885)

Main Inventor

Yang CHEN

Brief explanation

The present disclosure describes a semiconductor structure and a method for manufacturing it.

• The method begins with providing a substrate and forming a sacrificial dielectric layer on it.
• A part of the sacrificial dielectric layer is patterned along a first direction to create a series of first trenches in the layer.
• The first trenches are arranged at intervals along a second direction.
• Another part of the sacrificial dielectric layer and a portion of the substrate below it are patterned to create a series of second trenches below the first trenches.
• The second trenches have a predetermined depth in the substrate.
• A protective layer is then formed on the sidewalls of both the first and second trenches.
• Finally, bit line structures are formed in both the first and second trenches.

Abstract

Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: providing a substrate, and forming a sacrificial dielectric layer on the substrate; patterning a part of the sacrificial dielectric layer along a first direction, and forming a plurality of first trenches arranged at intervals along a second direction in the sacrificial dielectric layer; patterning a part of the sacrificial dielectric layer at bottoms of the first trenches and a part of the substrate below the part of the sacrificial dielectric layer, and forming a plurality of second trenches arranged at intervals below the first trenches, wherein the second trench has a preset depth in the substrate; forming a protective layer on sidewalls of the first trenches and sidewalls of the second trenches; and forming bit line structures in the first trenches and the second trenches.

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SEMICONDUCTOR STRUCTURE (18093779)

Main Inventor

Xiaojie LI

Brief explanation

The patent application describes a semiconductor structure and a method for forming the structure. 

• The method involves forming a stacking layer on a substrate, which includes multiple semiconductor layers arranged at intervals in one direction.
• The stacking layer also includes specific regions for transistors, capacitors, and bit lines.
• The semiconductor layers consist of semiconductor columns arranged at intervals in another direction.
• A capacitor is formed in the capacitor region, extending in a different direction.
• A word line is formed in the transistor region, covering the semiconductor columns and extending in the same direction as the columns.
• A bit line is formed in the bit line region, extending in the same direction as the stacking layer.

Abstract

This invention relates to a semiconductor structure and a method for forming the semiconductor structure. The method for forming a semiconductor structure includes the following steps: forming a stacking layer on a top surface of a substrate, where the stacking layer includes a plurality of semiconductor layers arranged at intervals in a first direction, and the stacking layer includes a transistor region, a capacitor region, and a bit line region, where the semiconductor layers include semiconductor columns arranged at intervals in a third direction; forming, in the capacitor region, a capacitor extending in the second direction; forming a word line in the transistor region, where the word line extends in the third direction and continuously covers the semiconductor columns arranged at intervals in the third direction; and forming a bit line in the bit line region, where the bit line extends in the first direction.

METHOD FOR FORMING CAPACITOR AND SEMICONDUCTOR DEVICE (18446507)

Main Inventor

Xiaoling WANG

Brief explanation

The patent application describes a method for forming a capacitor. Here are the key points:

• The method involves several steps to create the capacitor.
• A base is provided as the starting point.
• Layers called supporting layers and sacrificial layers are sequentially formed on the base.
• Through holes are created in the supporting and sacrificial layers to expose the base.
• These through holes are then filled to create filling structures.
• Another supporting layer is formed to cover the remaining sacrificial layer and filling structures.
• Through holes are created in this second supporting layer.
• A second sacrificial layer and a third supporting layer are formed, covering the second supporting layer and through holes.
• Through holes are created in the third supporting layer and second sacrificial layer.
• The filling structures created earlier are removed to connect the through holes in the third supporting layer with the corresponding ones in the first supporting layer.
• Finally, electrode layers, a dielectric layer, and a second electrode layer are sequentially formed to complete the capacitor.

Abstract

Method for forming a capacitor includes following operations. A base is provided. First supporting layer and first sacrificial layer are formed on the base sequentially. First through holes penetrating first supporting layer and first sacrificial layer are formed to expose the base. First through holes are filled to form first filling structures. Second supporting layer covering remaining first sacrificial layer and first filling structures is formed. Second through holes penetrating second supporting layer are formed. Second sacrificial layer covering remaining second supporting layer and second through holes, and third supporting layer are formed. Third through holes penetrating third supporting layer and second sacrificial layer are formed. First filling structures are removed to communicate each of third through holes and corresponding one of first through holes. First electrode layers, dielectric layer and second electrode layer covering first through holes and third through holes are formed sequentially to form the capacitor.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF (17816130)

Main Inventor

YOUMING LIU

Brief explanation

The present disclosure is about a semiconductor structure and its manufacturing method in the field of semiconductors.

• The manufacturing method involves several steps:

 * A first insulating layer is formed on a substrate.
 * Active pillars are arranged in the first insulating layer at regular intervals along two directions.
 * The first insulating layer is partially removed to create first trenches, exposing the substrate between adjacent active pillars.
 * An isolation layer is formed in each first trench.
 * Some of the first insulating layer between adjacent isolation layers is removed, creating a first filling space that exposes the middle region of the active pillar.
 * A gate structure is formed on the exposed peripheral surface of the active pillar, with the gate structures integrated along one direction.

The patent application aims to simplify the manufacturing process of semiconductor structures and improve their performance.

Abstract

The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors. The manufacturing method includes: forming a first insulating layer on a substrate, a plurality of active pillars are arranged at intervals along a first direction and a second direction in the first insulating layer; partially removing the first insulating layer, to form a plurality of first trenches, each first trench exposes the substrate, and is located between two adjacent columns of active pillars; forming an isolation layer in each first trench; removing at least a part of the first insulating layer between adjacent isolation layers, to form a first filling space, the first filling space exposes a peripheral surface of a middle region of the active pillar; and forming a gate structure on the exposed peripheral surface of the active pillar, the gate structures are integrated along the second direction.

MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR STRUCTURE, AND MEMORY (18363901)

Main Inventor

Yizhi ZENG

Brief explanation

The patent application describes a manufacturing method for a semiconductor structure and a memory.

• The method involves providing a substrate with an array region, a core region, and a boundary region.
• A first isolation layer is formed in the array region and a second-part boundary region.
• A first conductive layer is formed in the core region and a first-part boundary region.
• The first conductive layer is planarized to create a flat top surface.

Abstract

The present application provides a manufacturing method of a semiconductor structure, a semiconductor structure, and a memory. The manufacturing method of a semiconductor structure includes: providing a substrate, where the substrate includes an array region, a core region, and a boundary region located between the array region and the core region; forming a first isolation layer, where the first isolation layer is located in the array region and a second-part boundary region adjacent to the array region; and forming a first conductive layer, where the first conductive layer is located in the core region and a first-part boundary region adjacent to the core region. The first conductive layer is planarized to obtain a flat top surface.

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE (18446514)

Main Inventor

Shuai GUO

Brief explanation

The patent application is related to the semiconductor field and describes a semiconductor structure and a method for manufacturing it.

• The semiconductor structure includes a substrate with a bit line extending in one direction.
• An active pillar is located on the bit line, with its bottom surface in contact with the bit line. The active pillar is doped with an N-type element.
• An inversion region is present on the side surface of the active pillar and is doped with a P-type element.
• A dielectric layer and a word line extend in a different direction. The dielectric layer and the word line partially wrap around the inversion region.
• The dielectric layer is positioned between the word line and the inversion region.

Abstract

Embodiments of the disclosure relate to the semiconductor field, and provide a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a substrate that has a bit line extending in a first direction; an active pillar located on the bit line, in which a bottom surface of the active pillar is in contact with the bit line, and the active pillar is doped with an N-type element; an inversion region located on the side surface of the active pillar, and doped with a P-type element; a dielectric layer and a word line extending in a second direction, in which the dielectric layer and the word line wrap part of the inversion region, and the dielectric layer is located between the word line and the inversion region.

SEMICONDUCTOR STRUCTURE (17879913)

Main Inventor

Jianfeng XIAO

Brief explanation

The patent application describes a semiconductor structure consisting of a substrate and an active pillar located above it.

• The active pillar extends in a parallel direction to the substrate plane.
• The active pillar is composed of a body area and a peripheral area.
• The peripheral area includes a channel area.
• The channel area is doped with the same type of ions as the body area.
• The doping concentration of the channel area is higher than that of the body area.

Abstract

A semiconductor structure is provided. The semiconductor structure includes: a substrate and an active pillar located above the substrate. The active pillar extends in a first direction. The first direction is parallel to a plane where the substrate is located. The active pillar includes a body area extending in the first direction and a peripheral area surrounding the body area. The peripheral area includes a channel area. A type of doped ions of the channel area is the same as a type of doped ions of the body area, and a doping concentration of the channel area is greater than a doping concentration of the body area.

TRANSISTOR AND MANUFACTURING METHOD THEREOF, AND MEMORY (17816156)

Main Inventor

YOUMING LIU

Brief explanation

The patent application describes a transistor and its manufacturing method, as well as a memory, in the field of semiconductors.

• The transistor includes a channel with an accommodation space inside it.
• The gate of the transistor has two ends, with one end located inside the accommodation space and the other end located outside.
• A dielectric layer is positioned between the gate and the channel to insulate and isolate them.
• The transistor also includes a source at one end of the channel and a drain at the other end, both made of semiconductor material.
• The source, drain, and channel are arranged at intervals along the length direction of the channel.

Abstract

The present disclosure provides a transistor and a manufacturing method thereof, and a memory, relates to the technical field of semiconductors. The transistor includes: a channel, wherein an accommodation space is formed therein; a gate, provided with a first end and a second end that are opposite, wherein the first end of the gate is located inside the accommodation space, and the second end of the gate is located outside the accommodation space; a dielectric layer, located between the gate and a channel, insulating and isolating the gate and the channel; a source, provided at one end of the channel; and a drain, provided at the other end of the channel, wherein the drain and the source are arranged at intervals along a length direction of the channel, and the source, the drain, and the channel are each made of a semiconductor material.

TRANSISTOR AND MANUFACTURING METHOD THEREOF, AND MEMORY (17816435)

Main Inventor

YOUMING LIU

Brief explanation

The abstract describes a patent application related to a transistor and its manufacturing method, as well as a memory, in the field of semiconductors.

• The transistor includes a channel with multiple accommodation spaces.
• It has multiple gates with the same extension direction, each having a first end inside an accommodation space and a second end outside.
• A dielectric layer is located between the gate and the channel, providing insulation and isolation.
• The transistor also includes a source at one end of the channel and a drain at the other end, with a spacing between them.

Abstract

The present disclosure provides a transistor and a manufacturing method thereof, and a memory, and relates to the technical field of semiconductors. The transistor includes: a channel, wherein a plurality of accommodation spaces are formed therein; a plurality of gates, wherein the plurality of gates have a same extension direction and each have a first end and a second end that are opposite, the first end of the gate is located inside one of the accommodation spaces, and the second end of the gate is located outside the corresponding accommodation space; a dielectric layer, located between the gate and the channel, insulating and isolating the gate and the channel; a source, provided at one end of the channel; and a drain, provided at the other end of the channel, wherein the drain and the source are spaced apart.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF (17816436)

Main Inventor

YOUMING LIU

Brief explanation

The present disclosure is about a semiconductor structure and its manufacturing method in the field of semiconductors.

• The semiconductor structure includes a substrate and a memory cell array located on the substrate.
• The memory cell array consists of multiple transistor units, each having a first transistor and a second transistor connected to each other.
• The first and second transistors extend along a first direction parallel to the substrate.
• There is a first bit line that goes through the memory cell array and is connected to the first transistor.
• Similarly, there is a second bit line that goes through the memory cell array and is connected to the second transistor.
• The structure also includes a first word line connected to the first transistor and a second word line connected to the second transistor.

The patent application describes a semiconductor structure that simplifies the memory cell array and improves its functionality.

Abstract

The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a memory cell array, located on the substrate, the memory cell array includes a plurality of transistor units, each of the transistor units includes a first transistor and a second transistor extending along a first direction and electrically connected to each other, and the first direction is parallel to the substrate; a first bit line, penetrating the memory cell array and electrically connected to the first transistor; a second bit line, penetrating the memory cell array and electrically connected to the second transistor; a first word line, electrically connected to the first transistor; and a second word line, electrically connected to the second transistor.

METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE (17929842)

Main Inventor

Yi TANG

Brief explanation

The present disclosure is about a method of manufacturing a semiconductor structure and the structure itself.

• The method involves providing a base and forming active layers and sacrificial layers on the base.
• The active layers are arranged in groups with a specific distance between them.
• Isolation layers are then formed, which penetrate through all the active and sacrificial layers, dividing the active layers into multiple structures.
• In the word line region, some of the isolation and sacrificial layers are removed.

Abstract

Embodiments of the present disclosure relate to the field of semiconductors, and provide a method of manufacturing a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a base, and forming active layers and sacrificial layers on the base, wherein two adjacent ones of the active layers constitute an active group, there is a first distance between the active layers in the active group, there is a second distance between adjacent ones of active groups, and the first distance is greater than the second distance; forming isolation layers, wherein each isolation layer penetrates through all the active layers and all the sacrificial layers, and the isolation layers divide each of the active layers into a plurality of active structures; removing a part of the isolation layers in the word line region and a part of the sacrificial layers located in the word line region.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF (17813409)

Main Inventor

Youming Liu

Brief explanation

- The patent application describes a semiconductor structure and a manufacturing method in the field of semiconductors.

- The semiconductor structure includes a substrate and a first stacked structure that contains a memory cell array. - The structure also includes a plurality of word lines (WLs) arranged at intervals and extending along a first direction. - A plurality of bit lines (BLs) are also present, arranged at intervals and extending along a second direction. - One end of each BL forms a step in the first direction, and each BL has a groove on the surface of the step. - The second direction and the first direction intersect each other. - A plurality of BL plugs are arranged at intervals and extend along the first direction. - One end of each BL plug is placed in the groove of one of the BLs.

Abstract

The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors. The semiconductor structure includes: a substrate, a first stacked structure is disposed on the substrate, and includes a memory cell array; a plurality of word lines (WLs), arranged at intervals and extending along a first direction; a plurality of bit lines (BLs), arranged at intervals and extending along a second direction, one end of each of the plurality of BLs away from the memory cell array forms a step in the first direction, each BL is provided with a groove on a surface of the step, and the second direction and the first direction cross each other; and a plurality of BL plugs, arranged at intervals and extending along the first direction, one end of each BL plug is correspondingly disposed in the groove of one of the BLs.

MEMORY, SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME (17885727)

Main Inventor

Jingwen LU

Brief explanation

- The patent application is related to semiconductors and specifically focuses on memory.

- The method described in the patent involves providing a substrate with multiple conductive contact plugs and insulation layers. - Multiple capacitive layers are then stacked on the substrate surface in a perpendicular direction, with each layer containing capacitances connected to different contact plugs. - The method aims to increase the storage capacity of capacitances and improve product yield. - The innovation has potential benefits in terms of increased memory capacity and enhanced production efficiency.

Abstract

The disclosure relates to the technical field of semiconductors, and to a memory, a semiconductor structure and a method for same. The method includes: providing a substrate, the substrate including a plurality of conductive contact plugs in array distribution and insulation layers separating the conductive contact plugs; and forming a plurality of capacitive layers stacked and distributed in a direction perpendicular to the substrate on a surface of the substrate, each of the capacitive layers including a plurality of capacitances distributed at intervals, and the capacitances being respectively connected to different conductive contact plugs. According to the method, the storage capacity of capacitances can be increased, and product yield can be enhanced.

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME (18151360)

Main Inventor

Kanyu CAO

Brief explanation

The patent application describes a semiconductor structure consisting of a storage chip, a control chip, and a capacitor structure.

• The storage chip has an array area, while the control chip has a peripheral area.
• The storage chip and the control chip are connected together in a face-to-face bonding manner.
• The capacitor structure is located on the surface of the storage chip, away from the bonding surface.
• The capacitor structure includes capacitors that are electrically connected to corresponding transistors in the array area.

Abstract

A semiconductor structure includes a storage chip, a control chip, and a capacitor structure. The storage chip includes an array area. The control chip includes a peripheral area. The control chip and the storage chip are connected in a face-to-face bonding manner. The capacitor structure is located on a surface, away from a bonding surface, of the storage chip. The capacitor structure includes capacitors electrically connected to corresponding transistors in the array area.

SEMICONDUCTOR STRUCTURE AND METHOD FOR PREPARING SAME (17899684)

Main Inventor

Min LI

Brief explanation

The patent application describes a semiconductor structure and a method for preparing it.

• The method involves providing a substrate with active areas arranged in an array and an isolation structure separating the active areas.
• Buried word line structures are formed on one side of the substrate, close to the first surface, and embedded into the active areas.
• Bit line structures are formed on the first surface of the substrate and electrically connected to the active areas.
• Capacitor structures are formed on the second surface of the substrate and connected to the active areas in a one-to-one correspondence.

Abstract

A semiconductor structure and a method for preparing the same are provided. The method for preparing a semiconductor includes: providing a substrate including Active Areas (AAs) arranged in an array and an isolation structure separating the AAs, the substrate being provided with a first surface and a second surface opposite to each other; forming buried word line structures located on a side, close to the first surface, of the substrate and embedded into the AAs; forming bit line structures located on the first surface of the substrate and electrically connected to the AAs; and forming capacitor structures located on the second surface of the substrate and connected to the AAs in one-to-one correspondence.

TRANSISTOR, MANUFACTURING METHOD THEREOF, AND MEMORY (18151434)

Main Inventor

CHUN-WEI LIAO

Brief explanation

The patent application describes a transistor design that includes several key components:

• The transistor has a substrate with an active area.
• It includes a gate structure that goes through the active area and consists of a gate and a gate dielectric layer.
• The gate dielectric layer covers the sidewalls and bottom of the gate.
• A channel layer is located on the side of the gate dielectric layer opposite the gate.
• The channel layer contains a metal oxide semiconductor layer.
• The active area of the transistor includes a first active layer and a second active layer on either side of the gate structure.
• Both the first and second active layers are in contact with the channel layer.

This design aims to improve the performance and functionality of transistors by utilizing a metal oxide semiconductor layer in the channel layer and optimizing the contact between the active layers and the channel layer.

Abstract

A transistor includes: a substrate including an active area; a gate structure penetrating through the active area and including a gate and a gate dielectric layer, in which the gate dielectric layer covers sidewalls and a bottom of the gate; a channel layer located on a side of the gate dielectric layer away from the gate, in which the channel layer includes a metal oxide semiconductor layer, in which the active area includes a first active layer and a second active layer located at two sides of the gate structure, and the first active layer and the second active layer are in contact with the channel layer.

METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR STRUCTURE, AND MEMORY (18363819)

Main Inventor

Jingwen LU

Brief explanation

- The present disclosure describes a method of manufacturing a semiconductor structure and a memory.

- The semiconductor structure includes a base with columnar basal bodies and an isolation layer filled around them. - Word line trenches are present in the base, extending parallel to the surface of the base. - First trench portions are formed where the word line trenches intersect with the columnar basal bodies. - In the first trench portions, a first word line conductive layer, a second word line conductive layer, and an insulating layer are arranged sequentially from bottom to top. - Second trench portions are formed where the word line trenches intersect with the isolation layer. - In the second trench portions, the second word line conductive layer and the insulating layer are arranged sequentially from bottom to top.

Abstract

The present disclosure provides a method of manufacturing a semiconductor structure, a semiconductor structure, and a memory. The semiconductor structure includes a base. The base includes columnar basal bodies and an isolation layer filled around the columnar basal bodies. Word line trenches are provided in the base and extend along a direction parallel to a surface of the base. First trench portions are formed at parts of the word line trenches intersecting with the columnar basal bodies, and a first word line conductive layer, a second word line conductive layer, and an insulating layer are sequentially arranged in the first trench portions from bottom to top. Second trench portions are formed at parts of the word line trenches intersecting with the isolation layer, and the second word line conductive layer and the insulating layer are sequentially arranged in the second trench portions from bottom to top.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF (17816438)

Main Inventor

YOUMING LIU

Brief explanation

The present disclosure describes a semiconductor structure and a manufacturing method for semiconductors.

• The structure includes a substrate and a first stacked structure that contains a memory cell array.
• The first stacked structure also includes a plurality of word lines (WLs) that are electrically connected to the memory cell array.
• Additionally, there are a plurality of bit lines (BLs) that are located beside the first stacked structure and are also electrically connected to the memory cell array.
• Each BL has a step at one end away from the memory cell array and consists of a first core layer and a first conductive layer covering the core layer.
• The structure also includes a plurality of BL plugs, with each BL plug being in contact with the first conductive layer of one of the BLs.

Abstract

The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors, including: a substrate, a first stacked structure is disposed on the substrate, and the first stacked structure includes a memory cell array; a plurality of word lines (WLs), where the WL is disposed in the first stacked structure and is electrically connected to the memory cell array; a plurality of bit lines (BLs), the BL is disposed beside the first stacked structure, and is electrically connected to the memory cell array; and one end of each BL away from the memory cell array forms a step, and the BL includes a first core layer and a first conductive layer covering the first core layer; and a plurality of BL plugs, each BL plug is in corresponding contact with the first conductive layer of one of the BLs.

METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE (18363833)

Main Inventor

Jingwen LU

Brief explanation

The present disclosure describes a method of manufacturing a semiconductor structure and a semiconductor structure.

• The method involves starting with an initial structure that includes a substrate and initial word line structures, each containing an initial conductive structure.
• Isolation trenches are then formed to separate the remaining part of the substrate into multiple independent active area structures. These active area structures cover the first parts of the initial word line structures, while the isolation trenches expose the second parts of the initial word line structures.
• Finally, part of the second part of the initial word line structure is removed.

Abstract

The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure. The method includes: providing an initial structure, where the initial structure includes a substrate and initial word line structures, and each of the initial word line structures includes an initial conductive structure; forming isolation trenches, where a remaining part of the substrate is isolated by the isolation trenches to form a plurality of active area structures independent of each other, the active area structures cover first parts of the initial word line structures, and the isolation trenches expose second parts of the initial word line structures; and removing part of the second part of the initial word line structure.

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME (18169839)

Main Inventor

Chao LIN

Brief explanation

The abstract describes a semiconductor structure consisting of two bonded semiconductor layers with redistribution lines. The first layer has a redistribution line with a certain length on the bonding surface, while the second layer has a different length for its redistribution line on the same surface. The two redistribution lines are electrically connected to each other. The abstract also mentions a method for forming this semiconductor structure.

• Semiconductor structure with two bonded layers
• First layer has a redistribution line with a specific length on the bonding surface
• Second layer has a different length for its redistribution line on the same surface
• The redistribution lines are electrically connected
• Method for forming the semiconductor structure is provided

Abstract

A semiconductor structure includes a first semiconductor layer and a second semiconductor layer bonded to each other. The first semiconductor layer includes a first redistribution line, and the first redistribution line has a first projection length on a bonding surface of the first semiconductor layer and the second semiconductor layer. The second semiconductor layer includes a second redistribution line, and the second redistribution line has a second projection length on the bonding surface. The first projection length is different from the second projection length. The first redistribution line is electrically connected to the second redistribution line. A method for forming the same is also provided.