US Patent Application 17872479. METHOD AND DEVICE FOR EVALUATING PERFORMANCE OF SEQUENTIAL LOGIC ELEMENT simplified abstract

METHOD AND DEVICE FOR EVALUATING PERFORMANCE OF SEQUENTIAL LOGIC ELEMENT

Organization Name

CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor(s)

Zengquan Wu of HEFEI (CN)

METHOD AND DEVICE FOR EVALUATING PERFORMANCE OF SEQUENTIAL LOGIC ELEMENT - A simplified explanation of the abstract

This abstract first appeared for US patent application 17872479 titled 'METHOD AND DEVICE FOR EVALUATING PERFORMANCE OF SEQUENTIAL LOGIC ELEMENT

Simplified Explanation

- The patent application describes a method for evaluating the performance of a sequential logic element. - The method involves inputting a clock signal and a data signal to the sequential logic element to be tested. - The setup time of the sequential logic element is decremented from a first preset value to a second preset value based on a preset decrement step. - The first preset value is determined by the setup time when the sequential logic element outputs a target sampled value. - The second preset value is determined by the setup time when the sequential logic element outputs a reverse value of the target sampled value. - An evaluation parameter of the sequential logic element is determined based on the sampled value output by the sequential logic element after each decrement of the setup time. - The performance of the sequential logic element is evaluated based on the evaluation parameter.

Original Abstract Submitted

A method for evaluating performance of a sequential logic element includes: inputting a preset clock signal and a data signal to a sequential logic element to be tested; decrementing a setup time of the sequential logic element from a first preset value to a second preset value based on a preset decrement step, where the first preset value is determined by a setup time when the sequential logic element to be tested outputs a target sampled value, and the second preset value is determined by a setup time when the sequential logic element outputs a reverse value of the target sampled value; and determining an evaluation parameter of the sequential logic element based on a sampled value output by the sequential logic element after each decrement of the setup time, and evaluating performance of the sequential logic element based on the evaluation parameter of the sequential logic element to be tested.