US Patent Application 17898727. METHOD AND APPARATUS FOR CHECKING SIGNAL LINE simplified abstract
Contents
METHOD AND APPARATUS FOR CHECKING SIGNAL LINE
Organization Name
CHANGXIN MEMORY TECHNOLOGIES, INC.
Inventor(s)
METHOD AND APPARATUS FOR CHECKING SIGNAL LINE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17898727 titled 'METHOD AND APPARATUS FOR CHECKING SIGNAL LINE
Simplified Explanation
- The patent application describes a method and apparatus for checking a signal line in a circuit layout. - The method involves obtaining custom design information for a specific signal line in a circuit schematic. - Based on this information, a layout design rule is generated for the target signal line. - The circuit layout corresponding to the circuit schematic is then checked to see if the target signal line meets the layout design rule. - If the target signal line does not meet the layout design rule, a first label is added to indicate this. - The purpose of the first label is to identify that the target signal line does not comply with the layout design rule.
Original Abstract Submitted
A method and an apparatus for checking a signal line are provided. The method includes: obtaining custom design information of a target signal line in a circuit schematic, and generating a layout design rule corresponding to the target signal line based on the custom design information; checking whether the target signal line meets the layout design rule in a circuit layout corresponding to the circuit schematic; and adding a first label to a position of the target signal line in the circuit layout when the target signal line in the circuit layout does not meet the layout design rule. The first label is configured to indicate that the target signal line does not meet the layout design rule.
