US Patent Application 18150885. SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF simplified abstract

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SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Organization Name

CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor(s)

Yang Chen of Hefei City (CN)

Xinru Han of Hefei City (CN)

Shiran Zhang of Hefei City (CN)

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A simplified explanation of the abstract

This abstract first appeared for US patent application 18150885 titled 'SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Simplified Explanation

The present disclosure describes a semiconductor structure and a method for manufacturing it.

  • The method begins with providing a substrate and forming a sacrificial dielectric layer on it.
  • A part of the sacrificial dielectric layer is patterned along a first direction to create a series of first trenches in the layer.
  • The first trenches are arranged at intervals along a second direction.
  • Another part of the sacrificial dielectric layer and a portion of the substrate below it are patterned to create a series of second trenches below the first trenches.
  • The second trenches have a predetermined depth in the substrate.
  • A protective layer is then formed on the sidewalls of both the first and second trenches.
  • Finally, bit line structures are formed in both the first and second trenches.


Original Abstract Submitted

Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: providing a substrate, and forming a sacrificial dielectric layer on the substrate; patterning a part of the sacrificial dielectric layer along a first direction, and forming a plurality of first trenches arranged at intervals along a second direction in the sacrificial dielectric layer; patterning a part of the sacrificial dielectric layer at bottoms of the first trenches and a part of the substrate below the part of the sacrificial dielectric layer, and forming a plurality of second trenches arranged at intervals below the first trenches, wherein the second trench has a preset depth in the substrate; forming a protective layer on sidewalls of the first trenches and sidewalls of the second trenches; and forming bit line structures in the first trenches and the second trenches.

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