US Patent Application 18449060. SIGNAL SAMPLING CIRCUIT AND SEMICONDUCTOR MEMORY simplified abstract

SIGNAL SAMPLING CIRCUIT AND SEMICONDUCTOR MEMORY

Organization Name

CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor(s)

Zequn Huang of Hefei (CN)

SIGNAL SAMPLING CIRCUIT AND SEMICONDUCTOR MEMORY - A simplified explanation of the abstract

This abstract first appeared for US patent application 18449060 titled 'SIGNAL SAMPLING CIRCUIT AND SEMICONDUCTOR MEMORY

Simplified Explanation

The patent application describes a signal sampling circuit and a semiconductor memory.

• The signal sampling circuit samples a first CS signal and a first CA signal to obtain a second CS signal and a second CA signal.
• A logical operation circuit performs a logical operation on the first clock signal and the second CS signal.
• A command decoding circuit decodes and samples an initial command signal based on the second CS signal and the CS clock signal.
• An output combined circuit samples the second odd CA signal and the second even CA signal based on the even CS clock signal and the odd CS clock signal.
• The output combined circuit also samples the second odd CA signal and the second even CA signal based on the odd CS clock signal and the even CS clock signal.

Original Abstract Submitted

A signal sampling circuit and a semiconductor memory are provided. The signal sampling circuit includes: an input sampling circuit, configured to sample a first CS signal and a first CA signal according to a first clock signal to obtain a second CS signal and a second CA signal; a logical operation circuit, configured to perform a logical operation on the first clock signal and the second CS signal; a command decoding circuit, configured to decode and sample an initial command signal according to the second CS signal and the CS clock signal; and an output combined circuit, configured to: sample the second odd CA signal and the second even CA signal according to the even CS clock signal and the odd CS clock signal; and sample the second odd CA signal and the second even CA signal according to the odd CS clock signal and the even CS clock signal.