US Patent Application 17815623. SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF simplified abstract

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SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Organization Name

CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor(s)

Yi Tang of Hefei City (CN)

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A simplified explanation of the abstract

This abstract first appeared for US patent application 17815623 titled 'SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Simplified Explanation

The patent application describes a semiconductor structure and a method for manufacturing it.

  • The method involves providing a substrate with different regions.
  • A first stacked structure is formed on the substrate, consisting of a sacrificial layer and a semiconductor layer.
  • A second stacked structure is formed on top of the first stacked structure, also consisting of a sacrificial layer and a semiconductor layer.
  • An ion implantation process is performed on the semiconductor layers of both stacked structures.
  • The purpose of the invention is to provide a simplified and efficient method for manufacturing a semiconductor structure.


Original Abstract Submitted

Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The method includes: providing a substrate, wherein the substrate includes a word line region, a bit line region, and a capacitive region arranged adjacently; forming a first stacked structure that covers a surface of the substrate, wherein the first stacked structure includes a first sacrificial layer located on the surface of the substrate and a first semiconductor layer located on a surface of the first sacrificial layer; forming a second stacked structure that covers a surface of the first stacked structure, wherein the second stacked structure includes a second sacrificial layer located on the surface of the first stacked structure and a second semiconductor layer located on a surface of the second sacrificial layer; and performing an ion implantation on the first semiconductor layer and the second semiconductor layer.

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