SK hynix Inc. patent applications published on November 30th, 2023

Summary of the patent applications from SK hynix Inc. on November 30th, 2023

SK hynix Inc. has recently filed several patents related to resistive memory devices, semiconductor memory devices, memory device manufacturing methods, and semiconductor device fabrication methods. These patents aim to improve the performance, efficiency, and reliability of memory devices and semiconductor devices.

Summary: - SK hynix Inc. has filed patents for resistive memory devices with stack structures and slit structures, which are designed to improve memory block division and organization. - They have also filed patents for memory devices with stacked gate lines, main plugs, and plug separation patterns, which aim to enhance the structure and functionality of memory devices. - Additionally, SK hynix Inc. has filed patents for semiconductor memory devices with gate stacks, channel structures, core insulating layers, and barrier layers, which aim to improve the performance and efficiency of memory devices. - They have also filed patents for semiconductor memory devices with multiple stack structures, vertical structures, memory layers, channel patterns, and bit line contact structures, which aim to enhance the functionality and design of memory devices. - SK hynix Inc. has filed patents for methods of fabricating semiconductor devices, including the formation of sacrificial pads, etch target layers, openings, pillars, isolation trenches, and pad-type recesses, which aim to improve the fabrication process and structure of semiconductor devices. - They have also filed patents for electronic circuit board designs with multiple conductor layers, signal transmission pads, mesh structures, voids, and improved signal transmission and reception capabilities. - SK hynix Inc. has filed a patent for a controller with a storage memory, decoder, and processing circuit, which aims to improve the reliability of data decoding in a controller. - They have also filed a patent for a semiconductor wafer with chip sealing regions, scribe lane regions, chip guards, test circuit patterns, ground lines, and ground wiring layers, which aim to protect and test the chips on the wafer effectively. - Notable applications include resistive memory devices, semiconductor memory devices, memory device manufacturing methods, semiconductor device fabrication methods, electronic circuit board designs, and storage system designs.

Notable Applications:

• Resistive memory devices with stack structures and slit structures.
• Memory devices with stacked gate lines, main plugs, and plug separation patterns.
• Semiconductor memory devices with gate stacks, channel structures, core insulating layers, and barrier layers.
• Semiconductor memory devices with multiple stack structures, vertical structures, memory layers, channel patterns, and bit line contact structures.
• Methods of fabricating semiconductor devices, including sacrificial pads, etch target layers, openings, pillars, isolation trenches, and pad-type recesses.
• Electronic circuit board designs with multiple conductor layers, signal transmission pads, mesh structures, and voids.
• Controllers with storage memory, decoders, and processing circuits.
• Semiconductor wafers with chip sealing regions, scribe lane regions, chip guards, test circuit patterns, ground lines, and ground wiring layers.
• Storage systems with decoupling devices and unit capacitors.

Patent applications for SK hynix Inc. on November 30th, 2023

WAFER TEST SYSTEM AND OPERATING METHOD THEREOF (18052538)

Main Inventor

Dong Kil KIM

Brief explanation

The patent application describes a wafer test system that is used to test the electrical functionality of multiple dies on a wafer.

• The system includes a chuck that holds the wafer and a probe head that inputs a test signal and receives the corresponding test result.
• A probe card is used to input test signals to the individual dies on the wafer and receive the test results.
• A sensing device is mounted on the probe card to detect any active state occurring in the wafer during the electrical test.
• A determination unit receives the test result and the active state information and determines whether each die has failed based on this information.

The innovation in this patent application is the inclusion of a sensing device on the probe card to detect any active state occurring in the wafer during the electrical test. This allows for more accurate determination of whether a die has failed or not.

Abstract

A wafer test system includes a chuck for supporting a wafer including a plurality of dies, a probe head for inputting a test signal for an electrical test to the probe card and receiving an electrical test result corresponding to the test signal, a probe card for inputting test signals to the dies through a plurality of pins and receiving test result, a sensing device mounted on the surface of the probe card, for sensing an active state occurring in the wafer when the electrical test is performed, and a determination unit for receiving the electrical test result and the active state information for the dies and determining whether each of the dies has failed using the result of the electrical test on the wafer and active state information.

TEST CIRCUIT OF ELECTRONIC DEVICE, ELECTRONIC DEVICE INCLUDING TEST CIRCUIT, AND OPERATING METHOD THEREOF (17990119)

Main Inventor

Ki Hyuk SUNG

Brief explanation

The patent application describes a test circuit for an electronic device, along with the device itself and its operating method.

• The electronic device includes analog circuits and a control circuit.
• The control circuit connects various nodes in the analog circuits to an output terminal.
• A control signal generator generates a control signal based on an input signal from an external device to control the control circuit.
• A switching circuit is placed on the electrical path between the nodes and the control circuit.
• The switching circuit remains open for a specific amount of time after the voltage from an external power source is applied to the control circuit.

Abstract

Provided herein may be a test circuit of an electronic device, the electronic device including the test circuit, and an operating method thereof. The electronic device may include analog circuits, a control circuit configured to connect, to an output terminal, each of a plurality of nodes respectively included in the analog circuits to an output terminal, a control signal generator configured to generate a control signal for controlling the control circuit based on an input signal received from an external device, and a switching circuit disposed on an electrical path for connecting the plurality of nodes and the control circuit to each other and configured to be electrically open during a preset time amount from a time point at which a voltage from an external power source starts to be applied to the control circuit.

POWER SUPPLY APPARATUS AND METHOD AND STORAGE SYSTEM INCLUDING THE SAME (18073676)

Main Inventor

Woong Sik SHIN

Brief explanation

The patent application describes a power supply apparatus that includes power management circuits, a switch circuit, and a power controller.

• The power controller is responsible for driving the power management circuits in a specific sequence and controlling the switch circuit.
• The power management circuits are driven sequentially according to a drive sequence determined by the power controller.
• The switch circuit is controlled by the power controller to apply the output voltage of a normally operated power management circuit to the output terminals.
• The power management circuit that is currently being driven is selected as the source of power for the output terminals.
• This apparatus aims to provide a reliable and efficient power supply by sequentially driving the power management circuits and utilizing the output voltage of the selected circuit.

Abstract

A power supply apparatus may include a power management circuits, a switch circuit and a power controller. The power controller configured to sequentially drive the power management circuits in accordance with a drive sequence, and control the switch circuit to apply, to the output terminals, the output voltage of a normally operated power management circuit as the driven power management circuit among the power management circuits.

STORAGE DEVICE, ELECTRONIC DEVICE INCLUDING STORAGE DEVICE, AND OPERATING METHOD THEREOF (17978522)

Main Inventor

Byoung Min JIN

Brief explanation

- The patent application describes a storage device and an electronic device that includes the storage device, along with an operating method for the device.

- The storage device includes a memory controller with multiple functions that can be identified as separate storage devices by an external host. - A resource manager is included in the memory controller, which stores characteristic values and resource values corresponding to each of the functions. - A command processor is also part of the memory controller, and it processes commands from the external host based on the resource values of the functions. - The command processor prioritizes commands for the function with the lowest resource value and updates the resource value by accumulating the characteristic value of that function. - The purpose of this innovation is to efficiently manage and prioritize commands for different functions of the storage device based on their resource values.

Abstract

Provided herein may be a storage device, an electronic device including the storage device, and an operating method thereof. The storage device may include a memory controller, the memory controller including a plurality of functions configured to be identified as a plurality of storage devices logically separated from each other by an external host, a resource manager configured to store characteristic values and resource values respectively corresponding to the plurality of functions, and a command processor configured to, when commands respectively corresponding to the plurality of functions are received from the external host, preferentially process a command corresponding to a first function having lowest resource value, among the plurality of functions, based on the resource values, and update a resource value of the first function by accumulating an characteristic value of the first function in the resource value of the first function.

MEMORY CONTROLLER AND METHOD OF OPERATING THE SAME (18081605)

Main Inventor

Seon Ju LEE

Brief explanation

- The present technology is related to an electronic device and specifically a memory controller.

- The memory controller includes a latency monitor and an operation controller. - The latency monitor counts the number of over-latencies exceeding a reference value for requests from a host during each period. - It calculates the difference values between the over-latency count values of multiple periods and generates latency information. - The latency information includes the over-latency count values and the gaps between them. - The operation controller uses the latency information to determine if the gaps between certain periods exceed a threshold value. - Based on this determination, the operation controller delays the response to the requests accordingly.

Abstract

The present technology relates to an electronic device. According to the present technology, a memory controller may include a latency monitor and an operation controller. The latency monitor may count an over-latency count value representing a number of over-latencies exceeding a reference value among latencies for requests from a host during each of a plurality of periods, calculate gaps which are difference values between the over-latency count values of the plurality of periods, and generate latency information including the over-latency count values and the gaps. The operation controller may determine, based on the latency info oration, whether each gap between at least two target periods among the plurality of periods exceeds a threshold value, and delay a response to the requests according to a determination result.

MEMORY AND OPERATION METHOD THEREOF (17980141)

Main Inventor

Sang Woo YOON

Brief explanation

The abstract of the patent application describes an operation method for a memory. Here is a simplified explanation:

• The method involves receiving an active command and an active address.
• It determines if a row corresponding to the active address and a row corresponding to a target row address can be activated simultaneously.
• If they can be activated simultaneously, the method activates the row corresponding to the active address.
• It also activates the row corresponding to the target row address if it is determined that both rows can be activated simultaneously.

Bullet points explaining the patent/innovation:

• Memory operation method for efficient activation of rows in a memory.
• Allows for simultaneous activation of two rows in the memory.
• Improves memory access speed and efficiency.
• Reduces latency in memory operations.
• Enables faster data retrieval and storage in the memory.

Abstract

An operation method of a memory may include receiving an active command and an active address; determining whether a row corresponding to the active address and a row corresponding to a target row address are able to be substantially simultaneously activated; activating the row corresponding to the active address; and activating the row corresponding to the target row address in response to determining that the row corresponding to the active address and the row corresponding to the target row address are able to be substantially simultaneously activated.

STORAGE DEVICE AND OPERATING METHOD THEREOF (17987131)

Main Inventor

Ji Hoon HWANG

Brief explanation

The patent application describes a storage device that includes a memory device with multiple memory dies.

• Memory device has multiple memory dies

A calibration controller is included in the storage device to perform a calibration operation.

• Calibration controller performs a calibration operation

The calibration operation measures first to third calibration values for a data strobe signal at different temperatures.

• Calibration operation measures calibration values at different temperatures

A calibration register generates an equation between temperature and calibration value based on the measured values and stores a calibration table.

• Calibration register generates an equation and stores a calibration table

A memory interface in the storage device communicates with the memory device based on the calibration table.

• Memory interface communicates with memory device based on calibration table

Abstract

A storage device includes: a memory device including a plurality of memory dies; a calibration controller for performing a calibration operation of measuring first to third calibration values with respect to a data strobe signal at first to third temperatures of the storage device, respectively; a calibration register for generating an equation between a temperature and a calibration value based on the first to third calibration values and the first to third temperatures, and storing a calibration table based on the equation; and a memory interface for communicating with the memory device, based on the calibration table.

MEMORY SYSTEM FOR CONTROLLING OPERATING SPEED AND DATA PROCESSING SYSTEM INCLUDING THE SAME (17981653)

Main Inventor

Youn Won PARK

Brief explanation

The abstract describes a memory system that includes a memory device and a controller.

• The memory device has a non-volatile storage area where it stores a list of performance classes and a table of performance information.
• The performance classes represent different levels of performance, and the table contains performance parameter values for each class.
• The controller can provide the list of performance classes to an external device upon request.
• It can also select a performance class from the table based on a request from the external device.
• The controller then controls the operation of the memory device, adjusting the operation speed and method based on the performance parameter values corresponding to the selected class.

Abstract

A memory system comprising: a memory device configured to store, in a non-volatile storage area included therein, a list of a plurality of performance classes and a table of performance information representing a group of performance parameter values for each of the plurality of performance classes, and a controller configured to provide the list to an external device according to a first request received from the external device, select one of the plurality of performance classes within the table according to a second request received from the external device, and control an operation of the memory device at an operation speed and in an operation method according to the performance parameter values corresponding to the selected performance class.

PERIPHERAL COMPONENT INTERCONNECT EXPRESS INTERFACE DEVICE AND SYSTEM INCLUDING THE SAME (18446489)

Main Inventor

Yong Tae JEON

Brief explanation

The patent application describes a PCIe interface device that includes a NOP DLLP generator and a transmitter.

• The PCIe interface device generates a No Operation (NOP) data link layer packet (DLLP) in response to the occurrence of an event.
• The NOP DLLP includes event information representing the event.
• The device transmits the NOP DLLP to an external device through a link consisting of multiple lanes.

Abstract

Provided herein is a PCIe interface device. The PCIe interface device may include a NOP DLLP generator configured to generate a No Operation (NOP) data link layer packet (DLLP) including event information representing an event in response to the occurrence of the event and a transmitter configured to transmit the NOP DLLP to an external device through a link including a plurality of lanes.

CONTROLLER AND METHOD OF OPERATING THE SAME (17994908)

Main Inventor

Jung Ae KIM

Brief explanation

The abstract describes a controller for a semiconductor memory device that has multiple pages.

• The controller has a command generator that generates commands to control programming or reading operations of the memory device.
• The controller also has a data recovery manager that generates parity data for a weak page among the multiple pages in the memory device.
• The data recovery manager is able to recover data that was programmed to the weak page using the generated parity data.

Abstract

A controller controls a semiconductor memory device including a plurality of pages. The controller includes a command generator configured to generate a command for controlling a program operation or a read operation of a semiconductor memory device, and a data recovery manager configured to generate parity data corresponding to a weak page among a plurality of pages included in the semiconductor memory device and recover data programmed to the weak page.

MEMORY SYSTEM, MEMORY CONTROLLER AND OPERATING METHOD THEREOF FOR DETERMINING GARBAGE COLLECTION VICTIM BLOCK (17937334)

Main Inventor

Jung Woo KIM

Brief explanation

The patent application describes a memory system that includes a memory device and a memory controller.

• The memory device has multiple memory blocks, each containing multiple pages.
• The memory controller is responsible for managing the memory blocks and pages.
• The memory controller identifies "super memory blocks" that consist of two or more memory blocks.
• It calculates the number of valid pages in each super memory block.
• It determines a victim block for garbage collection based on the minimum valid page count and the average valid page count of the super memory blocks.
• The dispersion of valid page counts within the memory block groups in the super memory blocks is used to determine the victim block.

Abstract

A memory system may include a memory device including a plurality of memory blocks each including a plurality of pages and a memory controller. The memory controller may be configured to determine a plurality of super memory blocks each including two or more of the plurality of memory blocks, calculate valid page counts of each of the plurality of super memory blocks, and determine a victim block for garbage collection based on a minimum value among the valid page counts of the plurality of super memory blocks and average value of the valid page counts of the plurality of super memory blocks. Furthermore, a dispersion of valid page counts of memory block groups within the super memory blocks may be used to determine the victim block.

CONTROLLER AND METHOD OF OPERATING THE SAME (17983613)

Main Inventor

Myung Jin Jo

Brief explanation

The patent application describes a controller for a semiconductor memory device that operates based on requests from a host.

• The controller consists of a host interface, a first function block, a second function block, and an internal command cache.
• The host interface generates a first internal command in response to the request received from the host.
• The first function block generates a second internal command based on the first internal command.
• The second function block performs operations based on the second internal command.
• The internal command cache stores at least one internal command that corresponds to a reference internal command.

Abstract

A controller controls an operation of a semiconductor memory device based on a request received from a host. The controller includes a host interface, a first function block, a second function block, and an internal command cache. The host interface generates a first internal command in response to the request. The first function block generates a second internal command in response to the first internal command. The second function block operates in response to the second internal command. The internet command cache caches at least one internal command corresponding to a reference internal command.

DATA PROCESSING SYSTEM, OPERATING METHOD OF THE DATA PROCESSING SYSTEM, AND COMPUTING SYSTEM USING THE DATA PROCESSING SYSTEM AND OPERATING METHOD OF THE DATA PROCESSING SYSTEM (18077932)

Main Inventor

Seok Min LEE

Brief explanation

The patent application describes a data processing system that includes a processing memory with multiple sub-arrays and a controller that manages the memory.

• The system can detect a valid component from an input operand and apply a corresponding voltage to a row line in one or more sub-arrays.
• It can also store a second operand received from an external source in the sub-arrays.
• The purpose of this system is to efficiently process and store data in a memory system.

Abstract

A data processing system may include a processing memory including a plurality of sub-arrays, and a controller that controls the processing memory, detects a valid component from a first operand received from an exterior and having a digital level, applies a voltage corresponding to the valid component having a digital level to a row line of at least one sub-array, and stores a second operand received from an exterior in the at least one sub-array.

SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS CALIBRATING TERMINATION RESISTANCE (18449252)

Main Inventor

Sang Sic YOON

Brief explanation

The patent application describes a semiconductor system that includes a controller and a semiconductor device with two ranks.

• The controller outputs a command address, a first chip selection signal, and a second chip selection signal.
• The semiconductor device receives these signals and calibrates each termination resistance value based on them.
• When a write operation is performed on the first rank, the termination resistance value of the first rank is calibrated to a target resistance value based on the command address and the first chip selection signal.
• When a write operation is performed on the second rank, the termination resistance value of the first rank is calibrated to a dynamic resistance value based on the second chip selection signal.

Abstract

A semiconductor system according to an embodiment of the present disclosure includes a controller configured to output a command address, a first chip selection signal, and a second chip selection signal, and a semiconductor device, including a first rank and a second rank, configured to receive the command address, the first chip selection signal, and the second chip selection signal and configured to calibrate each termination resistance value based on the command address, the first chip selection signal, and the second chip selection signal. The first rank calibrates the termination resistance value of the first rank to a target resistance value based on the command address and the first chip selection signal when a write operation on the first rank is performed, and the first rank calibrates the termination resistance value of the first rank to a dynamic resistance value based on the second chip selection signal when a write operation on the second rank is performed.

SEMICONDUCTOR DEVICE FOR PERFORMING DATA ALIGNMENT OPERATION (17952008)

Main Inventor

Young Mok JEONG

Brief explanation

The patent application describes a semiconductor device that includes a circuit for generating alignment data from input data.

• The alignment data is generated by aligning latch data from different groups of input data with internal strobe signals.
• The aligned latch data is outputted as first and second alignment data.
• The device also includes a write data generation circuit that generates write data from the alignment data in synchronization with a latch clock.
• The write data is generated during different operation modes of the device.
• The first and second write data are generated from the alignment data during the first operation mode.
• During the second operation mode, only the first write data is generated from the alignment data.

Abstract

A semiconductor device includes an alignment data generation circuit aligning first and second latch data generated from a first group of input data in synchronization with a first internal strobe signal, outputting the aligned first and second latch data as first alignment data, aligning a first and second latch data generated from a second group of the input data in synchronization with a second internal strobe signal, and outputting the aligned first and second latch data as second alignment data. The semiconductor device includes a write data generation circuit generating first and second write data from the first and second alignment data in synchronization with a latch clock after the start of a first operation mode and generating the first and second write data from the first alignment data in synchronization with the latch clock after the start of a second operation mode.

APPARATUS FOR EVICTING COLD DATA FROM VOLATILE MEMORY DEVICE (17970103)

Main Inventor

Hyeong Tak JI

Brief explanation

The patent application describes a memory system that includes a non-volatile memory device, a volatile memory device, and a controller.

• The memory system is designed to store and manage data efficiently.
• The non-volatile memory device is used to store data that does not need to be accessed frequently.
• The volatile memory device is used to store data that needs to be accessed frequently.
• The volatile memory device performs a refresh operation on data stored in a word line multiple times, and then evicts the less frequently accessed data.
• The controller controls the operations of both the volatile and non-volatile memory devices.
• The controller is responsible for storing the evicted data into the non-volatile memory device.
• This memory system aims to optimize the usage of memory resources and improve overall system performance.

Abstract

A memory system may include: a non-volatile memory device, a volatile memory device suitable for defining, as cold data, data stored in a word line, on which a refresh operation is performed a number of times greater than a reference number among a plurality of word lines coupled to a volatile memory cell array, and evicting the cold data, and a controller suitable for controlling operations of the volatile memory device and the non-volatile memory device, and storing the evicted cold data into the non-volatile memory device.

SEMICONDUCTOR MEMORY DEVICE AND CONTROLLER FOR READING DATA WITH IMPROVED SPEED, AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE AND THE CONTROLLER (17962694)

Main Inventor

Sung Ho AHN

Brief explanation

The patent application describes a semiconductor memory device that includes a memory cell array, a peripheral circuit, and a control logic.

• The memory cell array consists of multiple memory cells.
• The peripheral circuit performs read operations on selected memory cells.
• The control logic is responsible for controlling the read operations of the peripheral circuit.
• The control logic receives a read command from an external device.
• The control logic determines whether to perform a discharge operation on word lines connected to the memory cells based on the type of read command received.

Abstract

A semiconductor memory device includes a memory cell array, a peripheral circuit, and a control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit performs a read operation on selected memory cells, among the plurality of memory cells. The control logic controls the read operation of the peripheral circuit in response to a read command that is received from an external device and determines whether to perform a discharge operation of word lines that are connected to the plurality of memory cells based on a type of the read command.

MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE (17986628)

Main Inventor

Hee Youl LEE

Brief explanation

This patent application describes a memory device and a method of operating the memory device. Here are the key points:

• The memory device includes a memory block with strings formed between bit lines and a source line.
• The device also includes a peripheral circuit that performs read operations on selected memory cells within selected strings.
• The peripheral circuit includes page buffers that increase the voltage of channels in the strings by applying a first precharge voltage to the bit lines during the set-up phase of the read operation.
• During the read phase of the operation, a second precharge voltage lower than the first precharge voltage is applied to the bit lines.
• In the discharge phase of the read operation, the bit lines are discharged.
• This method allows for efficient reading of memory cells in the memory device.

Abstract

A memory device, and a method of operating the memory device, includes a memory block including strings formed between bit lines and a source line and includes a peripheral circuit configured to perform a read operation of a selected memory cell included in a selected string among the strings. The peripheral circuit includes page buffers configured to increase a voltage of channels of the strings by applying a first precharge voltage to the bit lines in a set-up phase of the read operation, apply a second precharge voltage lower than the first precharge voltage to the bit lines in a read phase of the read operation, and discharge the bit lines in a discharge phase of the read operation.

MEMORY CONTROLLER AND OPERATING METHOD THEREOF (18060437)

Main Inventor

Seung Yeol LEE

Brief explanation

The patent application describes a memory controller that includes a test controller, a test information storage, and a machine learning processor.

• The test controller performs tests on a memory device using different test patterns and test modes with varying voltage and time conditions of test signals.
• The test information storage stores test result information, including values associated with fail bits of the memory device measured during the tests.
• The machine learning processor analyzes the test result information to detect a defect acceleration mode, which is a test mode that accelerates the detection of defects in the memory device.
• The machine learning processor uses the test result information and the target pattern to determine the defect acceleration mode.
• The memory controller aims to improve the efficiency and accuracy of testing memory devices by identifying the most effective test mode for detecting defects.

Abstract

A memory controller includes a test controller, a test information storage, and a machine learning processor. The test controller performs a test on a memory device using a target pattern selected from among a plurality of test patterns in each of a plurality of test modes in which voltage and time conditions of test signals are set differently. The test information storage stores test result information including values associated with fail bits of the memory device measured in the test. The machine learning processor detects a defect acceleration mode in which a defect of the memory device is accelerated, among the plurality of test modes, in the test performed using the target pattern on the basis of the test result information.

METHODS OF FORMING PATTERNS USING HARD MASK (18052813)

Main Inventor

Joo Hwan PARK

Brief explanation

- The patent application describes a method of forming patterns on a target layer.

- A hard mask layer is formed on the target layer. - A cleavage relief layer is coated on the hard mask layer to fill cleavages generated in the hard mask layer. - Photoresist patterns are formed on the cleavage relief layer. - Portions of the cleavage relief layer and portions of the hard mask layer are removed using the photoresist patterns as a first etch mask to form hard mask patterns. - Portions of the target layer are removed using the hard mask patterns as a second etch mask to form target layer patterns. - The hard mask patterns are then removed. - The hard mask layer includes an amorphous carbon layer (ACL). - The cleavage relief layer includes a spin-on carbon (SOC) layer.

Abstract

A method of forming patterns includes: forming a hard mask layer on a target layer, coating a cleavage relief layer on the hard mask layer to fill cleavages generated in the hard mask layer, forming photoresist patterns on the cleavage relief layer, removing portions of the cleavage relief layer and portions of the hard mask layer using the photoresist patterns as a first etch mask to form hard mask patterns, removing portions of the target layer using the hard mask patterns as a second etch mask to form target layer patterns, and removing the hard mask patterns. The hard mask layer includes an amorphous carbon layer (ACL), and the cleavage relief layer includes a spin-on carbon (SOC) layer.

SEMICONDUCTOR CHIP INCLUDING THROUGH ELECTRODE, AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME (18450216)

Main Inventor

Seung Hwan KIM

Brief explanation

The patent application describes a semiconductor chip with through electrodes arranged in an array region.

• The chip has a body part with a front surface and a rear surface.
• Through electrodes penetrate the body part and are arranged in a first direction in the array region.
• Front surface connection electrodes are coupled to the through electrodes over the front surface.
• Rear surface connection electrodes are coupled to the through electrodes over the rear surface.
• The array region includes a central region and edge regions on both sides of the central region.
• In the edge regions, the center of the front surface connection electrode and the center of the rear surface connection electrode are positioned farther from the central region than the center of the corresponding through electrode.

Abstract

A semiconductor chip includes a body part having a front surface and a rear surface, a plurality of through electrodes penetrating the body part and arranged in a first direction in an array region, a plurality of front surface connection electrodes respectively coupled to the through electrodes over the front surface of the body part, and a plurality of rear surface connection electrodes respectively coupled to the through electrodes over the rear surface of the body part. The array region includes a central region and edge regions positioned on both sides of the central region in the first direction. A center of the front surface connection electrode and a center of the rear surface connection electrode that are positioned in each of the edge regions are positioned at a distance farther from the central region than a center of the corresponding through electrode.

STORAGE SYSTEM INCLUDING A DECOUPLING DEVICE HAVING A PLURALITY OF UNIT CAPACITORS (18446959)

Main Inventor

Bok Kyu CHOI

Brief explanation

The patent application describes a storage system that includes a decoupling device with multiple unit capacitors.

• The storage system consists of a storage device, a control device, and a decoupling device.
• The storage device is responsible for receiving and storing data from the control device.
• The control device generates an inner voltage.
• The decoupling device is connected to the control device and is used to decouple the inner voltage.
• The decoupling device is made up of multiple unit capacitors that form several decoupling capacitors.
• Each unit capacitor comprises multiple capacitor elements, a first terminal, and a second terminal.
• The unit capacitors can be selectively connected to each other to create decoupling capacitors with different capacitances.

Abstract

Provided is a storage system including a decoupling device having a plurality of unit capacitors. The storage system includes a storage device, a control device, and a decoupling device disposed on a circuit substrate. The storage device is configured to receive and store data from the control device. The control device is configured to generate an inner voltage. The decoupling device is connected to the control device and decouples the inner voltage. The decoupling device includes a plurality of unit capacitors constituting a plurality of decoupling capacitors. Each of the unit capacitors includes a plurality of capacitor elements, a first terminal, and a second terminal. Some of the unit capacitors are selectively connected with each other to constitute the decoupling capacitors having various capacitances.

SEMICONDUCTOR WAFER INCLUDING CHIP GUARD (17978645)

Main Inventor

Heon Yong Chang

Brief explanation

The patent application describes a semiconductor wafer with specific features to protect and test the chips on the wafer.

• The wafer has a chip region where the chips are located, and a substrate where the chips are mounted.
• A first chip guard is placed over the substrate in a region called the chip sealing region, which is outside the chip region. This guard provides additional protection for the chips.
• A second chip guard is placed over the substrate in a region called the scribe lane region, which is outside the chip sealing region. This guard also provides protection for the chips.
• The scribe lane region also includes a test circuit pattern, which is used to test the chips on the wafer.
• The test circuit pattern includes a ground line that is connected to a ground well in the substrate. This helps in grounding the test circuit pattern.
• The second chip guard includes a ground wiring layer that is electrically connected to the ground line of the test circuit pattern. This ensures proper grounding of the test circuit pattern and enhances its functionality.

Abstract

A semiconductor wafer includes at least one chip region disposed in a substrate, a first chip guard disposed over the substrate in a chip sealing region positioned outside the at least one chip region, a second chip guard disposed over the substrate in a scribe lane region positioned outside the chip sealing region, and a test circuit pattern disposed in the scribe lane region and including a ground line electrically connected to a ground well in the substrate. The second chip guard includes a ground wiring layer electrically connected to the ground line of the test circuit pattern.

CONTROLLER AND OPERATING METHOD THEREOF FOR DETERMINING RELIABILITY DATA BASED ON SYNDROME WEIGHT (17960238)

Main Inventor

Dae Sung KIM

Brief explanation

The abstract describes a controller that includes a storage memory, a decoder, and a processing circuit.

• The storage memory stores N-bit read data and N reliability data units.
• The decoder performs a decoding operation on the read data using the reliability data units.
• The processing circuit determines the value of a reliability data unit based on the corresponding bit of the read data, the corresponding bit of another read data, and the difference between the syndrome weights of the two read data.
• The invention aims to improve the reliability of data decoding in a controller.

Abstract

A controller may include i) a storage memory configured to store N-bit read data and N reliability data units, ii) a decoder configured to execute a decoding operation for the read data based on the reliability data units, and iii) a processing circuit configured to determine a value of reliability data unit corresponding to I-th bit of read data based on an I-th bit of first read data, an I-th bit of second read data and a difference between first syndrome weight and second syndrome weight.

CIRCUIT BOARD (18073956)

Main Inventor

Jae Hoon KO

Brief explanation

- The patent application is for an electronic circuit board design.

- The circuit board includes multiple conductor layers stacked on top of each other. - The first conductor layer has a pad for transmitting and receiving signals to and from an external device. - The third conductor layer is stacked on top of the other layers and also transmits and receives signals to and from the external device. - One of the second conductor layers has a mesh structure and is electrically grounded. - The remaining second conductor layers have voids and are electrically opened. - The design aims to simplify the circuit board and improve signal transmission and reception.

Abstract

The present disclosure relates to an electronic circuit. A circuit board according to the present disclosure includes a first conductor layer including a first pad for transmitting and receiving a first signal to and from an external device, a plurality of second conductor layers stacked on the first conductor layer, and a third conductor layer stacked on the plurality of second conductor layers for transmitting and receiving a second signal to and from the external device, wherein at least one target conductor layer among the plurality of second conductor layers has a mesh structure and is electrically grounded, and remaining second conductor layers except for the at least one target conductor layer include respective voids and are electrically opened.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME (18073739)

Main Inventor

Jun Ha KWAK

Brief explanation

The patent application describes a method for fabricating a semiconductor device. 

• The method involves forming a sacrificial pad with multiple line portions and auxiliary lines over a lower structure.
• An etch target layer is then formed over the sacrificial pad.
• Multiple openings are created by etching the etch-target layer, stopping at the sacrificial pad.
• Pillars are formed to fill these openings.
• An isolation trench is formed by etching the etch-target layer, stopping at the sacrificial pad.
• Finally, a pad-type recess is created by removing the sacrificial pad through the isolation trench.

Abstract

A method for fabricating a semiconductor device includes: forming a sacrificial pad including a plurality of line portions and a plurality of auxiliary lines over a lower structure; forming an etch target layer over the sacrificial pad; forming a plurality of openings by etching the etch-target layer and stopping the etching at the sacrificial pad; forming a pillar filling the openings; forming an isolation trench by etching the etch-target layer and stopping the etching at the sacrificial pad; and forming a pad-type recess by removing the sacrificial pad through the isolation trench.

SEMICONDUCTOR MEMORY DEVICE (17989937)

Main Inventor

Kyu Jin CHOI

Brief explanation

The patent application describes a semiconductor memory device that includes two stack structures on a semiconductor substrate.

• The first stack structure and the second stack structure are made up of conductive layers stacked on the semiconductor substrate.
• The device also includes a first vertical structure and a second vertical structure, each with a memory layer and a channel pattern.
• The first vertical structure is in contact with the first stack structure, while the second vertical structure is in contact with the second stack structure.
• A first bit line contact structure is present on the first vertical structure, and a first bit line overlaps with the first bit line contact structure.
• The first bit line contact structure has a shape that widens towards the first bit line.

Abstract

A semiconductor memory device includes: a first stack structure and a second stack structure on a semiconductor substrate; a first vertical structure having a side all in contact with the first stack structure, the first vertical structure including a first memory layer and a first channel pattern; a second vertical structure having a sidewall in contact with the second stack structure, the second vertical structure including a second memory layer and a second channel pattern; a first bit line contact structure on the first vertical structure; and a first bit line overlapping with the first bit line contact structure. Each of the first stack structure and the second stack structure includes conductive layers stacked on the semiconductor substrate to be spaced apart from each other. The first bit line contact structure has a shape which is widened toward the first bit line.

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME (17990064)

Main Inventor

Jae Young OH

Brief explanation

- The patent application describes a semiconductor memory device and a method of manufacturing it.

- The semiconductor memory device includes a gate stack and a channel structure within the gate stack. - The channel structure consists of a channel layer with two portions: one that penetrates the gate stack and another that extends higher than the gate stack. - A core insulating layer is located in the central region of the channel structure. - A barrier layer is positioned between the channel layer and the core insulating layer. - The purpose of this design is to improve the performance and efficiency of the semiconductor memory device. - The method of manufacturing the device is not specified in the abstract.

Abstract

Provided herein may be a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device may include a gate stack, and a channel structure disposed in the gate stack, wherein the channel structure may include a channel layer including a first portion penetrating the gate stack and a second portion extending from the first portion to protrude higher than the gate stack, a core insulating layer disposed in a central region of the channel structure, and a barrier layer disposed between the channel layer and the core insulating layer.

MEMORY DEVICE AND MANUFACTURING METHOD OF THE MEMORY DEVICE (17991365)

Main Inventor

Byung In LEE

Brief explanation

The present disclosure is about a memory device and its manufacturing method.

• The memory device has a stacked structure with gate lines that are separated and stacked on top of each other.
• It also includes a main plug that is formed vertically to the stacked structure.
• A plug separation pattern is used to divide the main plug into first and second sub-plugs.
• There is a gap in the plug separation pattern.
• A separation layer surrounds the gap.

Abstract

The present disclosure relates to a memory device and a manufacturing method of the memory device. The memory device according to an embodiment includes a stacked structure including gate lines separated from and stacked on top of each other, a main plug formed in a vertical direction to the stacked structure, a plug separation pattern separating the main plug into first and second sub-plugs, a gap formed in the plug separation pattern; and a separation layer surrounding the gap.

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE (18446776)

Main Inventor

Min Jae HUR

Brief explanation

The patent application describes a semiconductor memory device with a stack structure and a slit structure.

• The stack structure consists of alternating insulation layers and conductive layers.
• The slit structure is designed to divide the stack structure into memory blocks.
• The part of the slit structure that defines one memory block has a dashed shape, including a slit region and a bridge region.

Abstract

A semiconductor memory device includes a stack structure and a slit structure. The stack structure includes insulation layers and conductive layers alternately stacked with the insulation layers. The slit structure is configured to divide the stack structure into memory blocks. A part of the slit structure configured to define one memory block has a dashed shape including a slit region and a bridge region.

RESISTIVE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME (17988267)

Main Inventor

In Ku KANG

Brief explanation

The present technology is about a resistive memory device and its manufacturing method.

• The resistive memory device consists of a stack structure with alternating interlayer insulating layers and conductive layers.
• The stack structure has a hole passing through it vertically.
• Along the sidewall of the hole, there is a sequence of a gate insulating layer, a channel layer, and a variable resistance layer.
• A high dielectric layer is formed between the channel layer and the gate insulating layer.
• The high dielectric layer is adjacent to the interlayer insulating layers in the stack structure.

Abstract

The present technology relates to a resistive memory device and a method of manufacturing the same. The resistive memory device includes a stack structure in which a plurality of interlayer insulating layers and a plurality of conductive layers are alternately stacked, a hole passing through the stack structure in a vertical direction, a gate insulating layer, a channel layer, and a variable resistance layer sequentially formed along a sidewall of the hole, and a high dielectric layer formed between the channel layer and the gate insulating layer, the high dielectric layer being adjacent to the plurality of interlayer insulating layers.