US Patent Application 17978645. SEMICONDUCTOR WAFER INCLUDING CHIP GUARD simplified abstract

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SEMICONDUCTOR WAFER INCLUDING CHIP GUARD

Organization Name

SK hynix Inc.

Inventor(s)

Heon Yong Chang of Gyeonggi-do (KR)

Sun Joo Park of Gyeonggi-do (KR)

SEMICONDUCTOR WAFER INCLUDING CHIP GUARD - A simplified explanation of the abstract

This abstract first appeared for US patent application 17978645 titled 'SEMICONDUCTOR WAFER INCLUDING CHIP GUARD

Simplified Explanation

The patent application describes a semiconductor wafer with specific features to protect and test the chips on the wafer.

  • The wafer has a chip region where the chips are located, and a substrate where the chips are mounted.
  • A first chip guard is placed over the substrate in a region called the chip sealing region, which is outside the chip region. This guard provides additional protection for the chips.
  • A second chip guard is placed over the substrate in a region called the scribe lane region, which is outside the chip sealing region. This guard also provides protection for the chips.
  • The scribe lane region also includes a test circuit pattern, which is used to test the chips on the wafer.
  • The test circuit pattern includes a ground line that is connected to a ground well in the substrate. This helps in grounding the test circuit pattern.
  • The second chip guard includes a ground wiring layer that is electrically connected to the ground line of the test circuit pattern. This ensures proper grounding of the test circuit pattern and enhances its functionality.


Original Abstract Submitted

A semiconductor wafer includes at least one chip region disposed in a substrate, a first chip guard disposed over the substrate in a chip sealing region positioned outside the at least one chip region, a second chip guard disposed over the substrate in a scribe lane region positioned outside the chip sealing region, and a test circuit pattern disposed in the scribe lane region and including a ground line electrically connected to a ground well in the substrate. The second chip guard includes a ground wiring layer electrically connected to the ground line of the test circuit pattern.

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