US Patent Application 18060437. MEMORY CONTROLLER AND OPERATING METHOD THEREOF simplified abstract

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MEMORY CONTROLLER AND OPERATING METHOD THEREOF

Organization Name

SK hynix Inc.

Inventor(s)

Seung Yeol Lee of Icheon-si (KR)

MEMORY CONTROLLER AND OPERATING METHOD THEREOF - A simplified explanation of the abstract

This abstract first appeared for US patent application 18060437 titled 'MEMORY CONTROLLER AND OPERATING METHOD THEREOF

Simplified Explanation

The patent application describes a memory controller that includes a test controller, a test information storage, and a machine learning processor.

  • The test controller performs tests on a memory device using different test patterns and test modes with varying voltage and time conditions of test signals.
  • The test information storage stores test result information, including values associated with fail bits of the memory device measured during the tests.
  • The machine learning processor analyzes the test result information to detect a defect acceleration mode, which is a test mode that accelerates the detection of defects in the memory device.
  • The machine learning processor uses the test result information and the target pattern to determine the defect acceleration mode.
  • The memory controller aims to improve the efficiency and accuracy of testing memory devices by identifying the most effective test mode for detecting defects.


Original Abstract Submitted

A memory controller includes a test controller, a test information storage, and a machine learning processor. The test controller performs a test on a memory device using a target pattern selected from among a plurality of test patterns in each of a plurality of test modes in which voltage and time conditions of test signals are set differently. The test information storage stores test result information including values associated with fail bits of the memory device measured in the test. The machine learning processor detects a defect acceleration mode in which a defect of the memory device is accelerated, among the plurality of test modes, in the test performed using the target pattern on the basis of the test result information.

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