US Patent Application 18449252. SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS CALIBRATING TERMINATION RESISTANCE simplified abstract
SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS CALIBRATING TERMINATION RESISTANCE
Organization Name
Inventor(s)
Sang Sic Yoon of Icheon-si Gyeonggi-do (KR)
Jung Taek You of Icheon-si Gyeonggi-do (KR)
SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS CALIBRATING TERMINATION RESISTANCE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18449252 titled 'SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS CALIBRATING TERMINATION RESISTANCE
Simplified Explanation
The patent application describes a semiconductor system that includes a controller and a semiconductor device with two ranks.
- The controller outputs a command address, a first chip selection signal, and a second chip selection signal.
- The semiconductor device receives these signals and calibrates each termination resistance value based on them.
- When a write operation is performed on the first rank, the termination resistance value of the first rank is calibrated to a target resistance value based on the command address and the first chip selection signal.
- When a write operation is performed on the second rank, the termination resistance value of the first rank is calibrated to a dynamic resistance value based on the second chip selection signal.
Original Abstract Submitted
A semiconductor system according to an embodiment of the present disclosure includes a controller configured to output a command address, a first chip selection signal, and a second chip selection signal, and a semiconductor device, including a first rank and a second rank, configured to receive the command address, the first chip selection signal, and the second chip selection signal and configured to calibrate each termination resistance value based on the command address, the first chip selection signal, and the second chip selection signal. The first rank calibrates the termination resistance value of the first rank to a target resistance value based on the command address and the first chip selection signal when a write operation on the first rank is performed, and the first rank calibrates the termination resistance value of the first rank to a dynamic resistance value based on the second chip selection signal when a write operation on the second rank is performed.
