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Category:G06F12/0897
Subcategories
This category has the following 33 subcategories, out of 33 total.
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Pages in category "G06F12/0897"
The following 103 pages are in this category, out of 103 total.
1
- 17957479. MULTI-LEVEL STARVATION WIDGET simplified abstract (ADVANCED MICRO DEVICES, INC.)
- 18091140. TIERED MEMORY CACHING simplified abstract (Advanced Micro Devices, Inc.)
- 18169852. PROCESSOR-BASED SYSTEM FOR ALLOCATING CACHE LINES TO A HIGHER-LEVEL CACHE MEMORY simplified abstract (QUALCOMM Incorporated)
- 18182772. Canceling Prefetch of Cache Blocks Based on an Address and a Bit Field simplified abstract (SiFive, Inc.)
- 18365595. SCHEDULING OF THREADS FOR EXECUTION UTILIZING LOAD BALANCING OF THREAD GROUPS simplified abstract (Intel Corporation)
- 18374951. Speculative Cache Invalidation for Processing-in-Memory Instructions (Advanced Micro Devices, Inc.)
- 18375018. Preemptive Flushing of Processing-in-Memory Data Structures (Advanced Micro Devices, Inc.)
- 18442660. METHODS AND APPARATUS TO FACILITATE ATOMIC OPERATIONS IN VICTIM CACHE simplified abstract (TEXAS INSTRUMENTS INCORPORATED)
- 18460772. TRACKING STREAMING ENGINE VECTOR PREDICATES TO CONTROL PROCESSOR EXECUTION simplified abstract (Texas Instruments Incorporated)
- 18463101. SLOT/SUB-SLOT PREFETCH ARCHITECTURE FOR MULTIPLE MEMORY REQUESTORS simplified abstract (Texas Instruments Incorporated)
- 18472936. USER CONTROLLED ALLOCATION OF A SPECIFIC CACHE LINE AT TIME OF ACCESS (International Business Machines Corporation)
- 18478855. DISAGGREGATED PROCESSOR ARCHITECTURES USING SELECTIVE TRANSFER TECHNOLOGY (INTEL CORPORATION)
- 18491474. INSTRUCTION BASED CONTROL OF MEMORY ATTRIBUTES simplified abstract (Intel Corporation)
- 18516716. SYSTEMS AND METHODS FOR UPDATING MEMORY SIDE CACHES IN A MULTI-GPU CONFIGURATION simplified abstract (Intel Corporation)
- 18581552. INSERTING PREDEFINED PAD VALUES INTO A STREAM OF VECTORS simplified abstract (TEXAS INSTRUMENTS INCORPORATED)
- 18584151. METHODS AND APPARATUS TO REDUCE READ-MODIFY-WRITE CYCLES FOR NON-ALIGNED WRITES simplified abstract (Texas Instruments Incorporated)
- 18587416. Multiple Multiplication Units in a Data Path simplified abstract (Texas Instruments Incorporated)
- 18620284. MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS simplified abstract (Intel Corporation)
- 18624301. PROCESSOR-BASED SYSTEM FOR ALLOCATING CACHE LINES TO A HIGHER-LEVEL CACHE MEMORY simplified abstract (QUALCOMM Incorporated)
- 18626775. Multi-tile Memory Management for Detecting Cross Tile Access Providing Multi-Tile Inference Scaling and Providing Page Migration simplified abstract (Intel Corporation)
- 18655454. CONVERTING A STREAM OF DATA USING A LOOKASIDE BUFFER simplified abstract (Texas Instruments Incorporated)
- 18659407. VICTIM CACHE WITH WRITE MISS MERGING simplified abstract (Texas Instruments Incorporated)
- 18660120. Method and Apparatus for Dual Issue Multiply Instructions simplified abstract (Texas Instruments Incorporated)
- 18674108. STREAMING ENGINE WITH ERROR DETECTION, CORRECTION AND RESTART simplified abstract (Texas Instruments Incorporated)
- 18793247. MULTI-TILE MEMORY MANAGEMENT (Intel Corporation)
- 18812008. METHOD AND APPARATUS FOR VECTOR PERMUTATION (TEXAS INSTRUMENTS INCORPORATED)
- 18818738. METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SYSTEM (TEXAS INSTRUMENTS INCORPORATED)
- 18822571. CACHE CONTROL CIRCUIT WITH FETCH HYSTERESIS (TEXAS INSTRUMENTS INCORPORATED)
- 18906428. CACHE STRUCTURE AND UTILIZATION (Intel Corporation)
- 18906859. SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE (Intel Corporation)
- 18915492. MULTI-TILE MEMORY MANAGEMENT (Intel Corporation)
- 18947337. CONSISTENT FILE SYSTEM SEMANTICS WITH CLOUD OBJECT STORAGE (Oracle International Corporation)
- 18948174. SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION (Intel Corporation)
- 18966252. METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRITE MERGING (Texas Instruments Incorporated)
- 18966268. FULLY PIPELINED READ-MODIFY-WRITE SUPPORT (Texas Instruments Incorporated)
- 18973226. TRACKING STREAMING ENGINE VECTOR PREDICATES TO CONTROL PROCESSOR EXECUTION (TEXAS INSTRUMENTS INCORPORATED)
A
- Advanced micro devices, inc. (20240111684). MULTI-LEVEL STARVATION WIDGET simplified abstract
- Advanced micro devices, inc. (20250110886). Speculative Cache Invalidation for Processing-in-Memory Instructions
- Advanced micro devices, inc. (20250110887). Preemptive Flushing of Processing-in-Memory Data Structures
- Advanced Micro Devices, Inc. patent applications on April 3rd, 2025
- ADVANCED MICRO DEVICES, INC. patent applications on April 4th, 2024
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- Intel corporation (20240104022). MULTI-LEVEL CACHE DATA TRACKING AND ISOLATION simplified abstract
- Intel corporation (20240184739). DYNAMIC MEMORY RECONFIGURATION simplified abstract
- Intel corporation (20240256483). GRAPHICS PROCESSOR DATA ACCESS AND SHARING simplified abstract
- Intel corporation (20240320184). MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS simplified abstract
- Intel corporation (20240345990). Multi-tile Memory Management for Detecting Cross Tile Access Providing Multi-Tile Inference Scaling and Providing Page Migration simplified abstract
- Intel corporation (20240403259). COMPRESSION TECHNIQUES
- Intel corporation (20240403259). COMPRESSION TECHNIQUES simplified abstract
- Intel corporation (20240411717). CACHE STRUCTURE AND UTILIZATION
- Intel corporation (20250004981). MULTI-TILE MEMORY MANAGEMENT
- Intel corporation (20250103546). CACHE STRUCTURE AND UTILIZATION
- Intel corporation (20250103547). SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE
- Intel corporation (20250103548). SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION
- Intel corporation (20250112204). DISAGGREGATED PROCESSOR ARCHITECTURES USING SELECTIVE TRANSFER TECHNOLOGY
- Intel corporation (20250117356). MULTI-TILE MEMORY MANAGEMENT
- Intel Corporation patent applications on April 10th, 2025
- Intel Corporation patent applications on April 3rd, 2025
- INTEL CORPORATION patent applications on April 3rd, 2025
- Intel Corporation patent applications on August 1st, 2024
- Intel Corporation patent applications on December 12th, 2024
- Intel Corporation patent applications on December 5th, 2024
- Intel Corporation patent applications on January 23rd, 2025
- Intel Corporation patent applications on January 2nd, 2025
- Intel Corporation patent applications on January 30th, 2025
- Intel Corporation patent applications on June 6th, 2024
- Intel Corporation patent applications on March 14th, 2024
- Intel Corporation patent applications on March 27th, 2025
- Intel Corporation patent applications on March 28th, 2024
- Intel Corporation patent applications on October 17th, 2024
- Intel Corporation patent applications on September 26th, 2024
- International business machines corporation (20250103507). USER CONTROLLED ALLOCATION OF A SPECIFIC CACHE LINE AT TIME OF ACCESS
- International Business Machines Corporation patent applications on March 27th, 2025
- International Business Machines Corporation patent applications on March 6th, 2025
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- Qualcomm incorporated (20240202131). PROCESSOR-BASED SYSTEM FOR ALLOCATING CACHE LINES TO A HIGHER-LEVEL CACHE MEMORY simplified abstract
- Qualcomm incorporated (20240248851). PROCESSOR-BASED SYSTEM FOR ALLOCATING CACHE LINES TO A HIGHER-LEVEL CACHE MEMORY simplified abstract
- QUALCOMM Incorporated patent applications on July 25th, 2024
- QUALCOMM Incorporated patent applications on June 20th, 2024
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- Texas instruments incorporated (20240296050). CONVERTING A STREAM OF DATA USING A LOOKASIDE BUFFER simplified abstract
- Texas instruments incorporated (20240296129). VICTIM CACHE WITH WRITE MISS MERGING simplified abstract
- Texas instruments incorporated (20240311313). Method and Apparatus for Dual Issue Multiply Instructions simplified abstract
- Texas instruments incorporated (20240320094). STREAMING ENGINE WITH ERROR DETECTION, CORRECTION AND RESTART simplified abstract
- Texas instruments incorporated (20240411559). VARIABLE LATENCY INSTRUCTIONS
- Texas instruments incorporated (20240411703). PROCESSOR ARCHITECTURE WITH MEMORY ACCESS CIRCUIT
- Texas instruments incorporated (20250094358). METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRITE MERGING
- Texas instruments incorporated (20250094359). FULLY PIPELINED READ-MODIFY-WRITE SUPPORT
- Texas instruments incorporated (20250103510). TRACKING STREAMING ENGINE VECTOR PREDICATES TO CONTROL PROCESSOR EXECUTION
- Texas Instruments Incorporated patent applications on December 12th, 2024
- Texas Instruments Incorporated patent applications on February 1st, 2024
- TEXAS INSTRUMENTS INCORPORATED patent applications on January 23rd, 2025
- Texas Instruments Incorporated patent applications on January 30th, 2025
- Texas Instruments Incorporated patent applications on March 20th, 2025
- TEXAS INSTRUMENTS INCORPORATED patent applications on March 27th, 2025
- Texas Instruments Incorporated patent applications on September 19th, 2024
- Texas Instruments Incorporated patent applications on September 26th, 2024
- Texas Instruments Incorporated patent applications on September 5th, 2024