Intel Corporation patent applications on January 23rd, 2025
Patent Applications by Intel Corporation on January 23rd, 2025
Intel Corporation: 18 patent applications
Intel Corporation has applied for patents in the areas of H01L29/66 (4), H01L29/423 (3), G06F9/30 (3), G06F12/0895 (2), H01L21/28 (2) G06F3/0622 (1), H01L23/5222 (1), H01L27/1211 (1), H10B12/30 (1), H04L45/748 (1)
With keywords such as: structure, layer, metal, disposed, dielectric, semiconductor, voltage, gate, substrate, and memory in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): Ilya Alexandrovich of Yokneam Illit (IL) for intel corporation, Vladimir Beker of Ariel (IL) for intel corporation, Gideon Gerzon of Zichron Yaakov (IL) for intel corporation, Vincent R. Scarlata of Beaverton OR (US) for intel corporation
IPC Code(s): G06F3/06, G06F13/16, G06F13/40, G06F21/78, G06F21/79, G06F21/85
CPC Code(s): G06F3/0622
Abstract: an integrated circuit includes protected container access control logic to perform a set of access control checks and to determine whether to allow a device protected container module (dpcm) and an input and/or output (i/o) device to communicate securely through one of direct memory access (dma) and memory-mapped input/output (mmio). the dpcm and the i/o device are allowed to communicate securely if it is determined that at least the dpcm and the i/o device are mapped to one another, an access address associated with the communication resolves into a protected container memory, and a page of the protected container memory into which the access address resolves allows for the aforementioned one of dma and mmio. in some cases, a security attributes of initiator (sai) or security identifier may be used to obtain a dpcm identifier or attest that access is from a dpcm mapped to the i/o device. in some cases, a determination may be made that a type of access is compatible with one or more allowed access types for the page as represented in a protected container page metadata structure.
20250028532. DIRECT, UNCONDITIONAL JUMP_simplified_abstract_(intel corporation)
Inventor(s): Jason AGRON of San Jose CA (US) for intel corporation, Andreas KLEEN of Portland OR (US) for intel corporation, Ching-Tsun CHOU of Palo Alto CA (US) for intel corporation, Jonathan COMBS of Austin TX (US) for intel corporation, Hongjiu LU of Santa Clara CA (US) for intel corporation, Jared Warner STARK, IV of Portland OR (US) for intel corporation, Jeff WIEDEMEIER of Austin TX (US) for intel corporation
IPC Code(s): G06F9/30
CPC Code(s): G06F9/30054
Abstract: techniques for performing an unconditional jump are described. in some examples, an instruction is processed to perform the unconditional jump. in some examples, the instruction is to at least include one or more fields for an opcode and a 64-bit bit immediate, wherein the 64-bit immediate is to encode an absolute address and the opcode is to indicate execution circuitry is jump to the absolute address.
20250028533. ZERO-CLEARING SCALAR MOVES_simplified_abstract_(intel corporation)
Inventor(s): John MORGAN of Snoqualmie WA (US) for intel corporation, Michael ESPIG of Newberg OR (US) for intel corporation, Deepti AGGARWAL of Gilbert AZ (US) for intel corporation
IPC Code(s): G06F9/30
CPC Code(s): G06F9/30145
Abstract: techniques for zero clearing scalar moves are described. for example, one or more instructions are supported which, when executed, are to cause a scalar move of a 16-bit or 32-bit floating-point value from a source to a destination. when the destination is a vector register, all other data elements are to be zeroed.
Inventor(s): Debabrata Mohapatra of San Jose CA (US) for intel corporation, Arnab Raha of San Jose CA (US) for intel corporation, Deepak Mathaikutty of Chandler AZ (US) for intel corporation, Raymond Sung of San Francisco CA (US) for intel corporation, Cormac Brick of San Francisco CA (US) for intel corporation
IPC Code(s): G06F9/50, G06F7/50, G06F9/48, G06F15/80, G06F15/82, G06N20/00
CPC Code(s): G06F9/5027
Abstract: embodiments of the present disclosure are directed toward techniques and configurations enhancing the performance of hardware (hw) accelerators. the present disclosure provides a schedule-aware, dynamically reconfigurable, tree-based partial sum accumulator architecture for hw accelerators, wherein the depth of an adder tree in the hw accelerator is dynamically based on a dataflow schedule generated by a compiler. the adder tree depth is adjusted on a per-layer basis at runtime. configuration registers, programmed via software, dynamically alter the adder tree depth for partial sum accumulation based on the dataflow schedule. by facilitating a variable depth adder tree during runtime, the compiler can choose a compute optimal dataflow schedule that minimizes the number of compute cycles needed to accumulate partial sums across multiple processing elements (pes) within a pe array of a hw accelerator. other embodiments may be described and/or claimed.
Inventor(s): Neta Zmora of Tzur Moshe (IL) for intel corporation, Eran Ben-Avi of Haifa (IL) for intel corporation
IPC Code(s): G06F12/128, G06F12/084, G06F12/0895, G06N3/044, G06N3/045, G06N3/063, G06N3/084, G06N20/00
CPC Code(s): G06F12/128
Abstract: in an example, an apparatus comprises a plurality of compute engines; and logic, at least partially including hardware logic, to detect a cache line conflict in a last-level cache (llc) communicatively coupled to the plurality of compute engines; and implement context-based eviction policy to determine a cache way in the cache to evict in order to resolve the cache line conflict. other embodiments are also disclosed and claimed.
Inventor(s): JOYDEEP RAY of Folsom CA (US) for intel corporation, SELVAKUMAR PANNEER of Portland OR (US) for intel corporation, SAURABH TANGRI of Folsom CA (US) for intel corporation, BEN ASHBAUGH of Folsom CA (US) for intel corporation, SCOTT JANUS of Loomis CA (US) for intel corporation, ABHISHEK APPU of El Dorado Hills CA (US) for intel corporation, VARGHESE GEORGE of Folsom CA (US) for intel corporation, RAVISHANKAR IYER of Portland OR (US) for intel corporation, NILESH JAIN of Portland OR (US) for intel corporation, PATTABHIRAMAN K of Bangalore (IN) for intel corporation, ALTUG KOKER of El Dorado Hills CA (US) for intel corporation, MIKE MACPHERSON of Portland OR (US) for intel corporation, JOSH MASTRONARDE of Sacramento CA (US) for intel corporation, ELMOUSTAPHA OULD-AHMED-VALL of Chandler AZ (US) for intel corporation, JAYAKRISHNA P. S of Bangalore (IN) for intel corporation, ERIC SAMSON of Folsom CA (US) for intel corporation
IPC Code(s): G06F15/78, G06F7/544, G06F7/575, G06F7/58, G06F9/30, G06F9/38, G06F9/50, G06F12/02, G06F12/06, G06F12/0802, G06F12/0804, G06F12/0811, G06F12/0862, G06F12/0866, G06F12/0871, G06F12/0875, G06F12/0882, G06F12/0888, G06F12/0891, G06F12/0893, G06F12/0895, G06F12/0897, G06F12/1009, G06F12/128, G06F15/80, G06F17/16, G06F17/18, G06N3/08, G06T1/20, G06T1/60, G06T15/06, H03M7/46
CPC Code(s): G06F15/7839
Abstract: embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. one embodiment provides a multi-gpu architecture with uniform latency. one embodiment provides techniques to distribute memory output based on memory chip thermals. one embodiment provides techniques to enable thermally aware workload scheduling. one embodiment provides techniques to enable end to end contracts for workload scheduling on multiple gpus.
20250028965. WEIGHT QUANTIZATION ADAPTATION TECHNOLOGY_simplified_abstract_(intel corporation)
Inventor(s): Alexander Kozlov of Dubai (AE) for intel corporation, Andrey Anufriev of Taufkirchen (DE) for intel corporation, Nikolay Lyalyushkin of Munich (DE) for intel corporation, Dmitry Gorokhov of Dubai (AE) for intel corporation, Yury Gorbachev of Novgorod (RU) for intel corporation
IPC Code(s): G06N3/082
CPC Code(s): G06N3/082
Abstract: systems, apparatuses and methods may provide for technology that selects a subset of linear layers from a plurality of linear layers in a pre-trained artificial intelligence (ai) model, wherein a quantization error of the subset of linear layers exceeds an error threshold. for each linear layer in the subset of linear layers, the technology solves a singular value decomposition (svd) approximation, generates a first adapter layer and a second adapter layer based on the svd decomposition, wherein the first adapter layer and the second adapter layer include weight matrices having a first dimension that is less than a first rank threshold and a second dimension that is greater than a second rank threshold, and determines an inference output based on the linear layer, the first adapter layer and the second adapter layer.
Inventor(s): Joanna Douglas of Hillsboro OR (US) for intel corporation, Michal Taryma of Hillsboro OR (US) for intel corporation, Mario Garcia of Hillsboro OR (US) for intel corporation, Carlos Dominguez of Hillsboro OR (US) for intel corporation
IPC Code(s): G06T15/00, G06T1/20, G06T3/4053, G06T15/50
CPC Code(s): G06T15/005
Abstract: systems and methods for super sampling and viewport shifting of non-real time 3d applications are disclosed. in one embodiment, a graphics processing unit includes a processing resource to execute graphics commands to provide graphics for an application, a capture tool to capture the graphics commands, and a data generator to generate a dataset including at least one frame based on the captured graphics commands and to modify viewport settings for each frame of interest to generate a conditioned dataset.
Inventor(s): Conor P. PULS of Portland OR (US) for intel corporation, Giorgio MARIOTTINI of Hillsboro OR (US) for intel corporation, Brenden ARRUDA of Hillsboro OR (US) for intel corporation, Shawna M. LIFF of Scottsdale AZ (US) for intel corporation, Lei JIANG of Camas WA (US) for intel corporation, Samson ODUNUGA of Sherwood OR (US) for intel corporation, Gerardo MONTANO of Hillsboro OR (US) for intel corporation, Hannes GREVE of Portland OR (US) for intel corporation, Apratim DHAR of Portland OR (US) for intel corporation, Aaron M. WHITE of Beaverton OR (US) for intel corporation
IPC Code(s): H01L23/48, H01L27/092, H01L29/06, H01L29/423, H01L29/78
CPC Code(s): H01L23/481
Abstract: structures having a through-stack thermal sink for dual-sided devices are described. in an example, an integrated circuit structure includes a front side structure. the front side structure includes a device layer having a plurality of fin-based or nanowire-based transistors, and a plurality of metallization layers above the plurality of fin-based or nanowire-based transistors. a backside structure is below the plurality of fin-based or nanowire-based transistors. a carrier wafer or substrate is bonded to the front side structure. a thermal conductive via extends from a location at a bottom of or below the plurality of fin-based or nanowire-based transistors to a location on or into the carrier wafer or substrate.
Inventor(s): Arnab SARKAR of Chandler AZ (US) for intel corporation, Sujit SHARAN of Chandler AZ (US) for intel corporation, Dae-Woo KIM of Phoenix AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L21/66, H01L23/00, H01L23/544, H01L23/58, H01L25/065, H01L25/18
CPC Code(s): H01L23/49827
Abstract: guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. in an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. a metallization structure is disposed on the insulating layer. the metallization structure incudes conductive routing disposed in a dielectric material stack. the semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. the first metal guard ring includes a plurality of individual guard ring segments. the semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.
Inventor(s): Leonard P. Guler of Hillsboro OR (US) for intel corporation, Charles Henry Wallace of Portland OR (US) for intel corporation, Paul A. Nyhus of Portland OR (US) for intel corporation
IPC Code(s): H01L23/522, G06F1/16, H01L21/768, H01L23/14, H01L23/50, H01L23/528
CPC Code(s): H01L23/5222
Abstract: methods for fabricating an ic structure, e.g., for fabricating a metallization stack portion of an ic structure, as well as related semiconductor devices, are disclosed. an example fabrication method includes splitting metal lines that are supposed to be included at a tight pitch in a single metallization layer into two vertically-stacked layers (hence the term âvertical metal splittingâ) by using helmets and wrap-around dielectric spacers. metal lines split into two such layers may be arranged at a looser pitch in each layer, compared to the pitch at which metal lines of the same size would have to be arranged if there were included in a single layer. increasing the pitch of metal lines may advantageously allow decreasing the parasitic metal-to-metal capacitance associated with the metallization stack.
Inventor(s): Bernhard SELL of Portland OR (US) for intel corporation, Oleg GOLONZKA of Beaverton OR (US) for intel corporation
IPC Code(s): H01L23/535, H01L21/28, H01L21/768, H01L21/8234, H01L23/485, H01L23/522, H01L23/528, H01L23/532, H01L27/088, H01L29/08, H01L29/417, H01L29/49, H01L29/66, H01L29/78
CPC Code(s): H01L23/535
Abstract: methods and associated structures of forming a microelectronic device are described. those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ild disposed on a top surface of a metal gate disposed on the substrate.
Inventor(s): Sanka GANESAN of Chandler AZ (US) for intel corporation, Kevin MCCARTHY of Tempe AZ (US) for intel corporation, Leigh M. TRIBOLET of Chandler AZ (US) for intel corporation, Debendra MALLIK of Chandler AZ (US) for intel corporation, Ravindranath V. MAHAJAN of Chandler AZ (US) for intel corporation, Robert L. SANKMAN of Phoenix AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L21/48, H01L21/56, H01L21/683, H01L23/00, H01L23/31, H01L23/367, H01L23/498, H01L25/00, H01L25/065
CPC Code(s): H01L23/5381
Abstract: embodiments include semiconductor packages and methods to form the semiconductor packages. a semiconductor package includes a bridge over a glass patch. the bridge is coupled to the glass patch with an adhesive layer. the semiconductor package also includes a high-density packaging (hdp) substrate over the bridge and the glass patch. the hdp substrate is conductively coupled to the glass patch with a plurality of through mold vias (tmvs). the semiconductor package further includes a plurality of dies over the hdp substrate, and a first encapsulation layer over the tmvs, the bridge, the adhesive layer, and the glass patch. the hdp substrate includes a plurality of conductive interconnects that conductively couple the dies to the bridge and glass patch. the bridge may be an embedded multi-die interconnect bridge (emib), where the emib is communicatively coupled to the dies, and the glass patch includes a plurality of through glass vias (tgvs).
Inventor(s): Thomas BROWN of Portland OR (US) for intel corporation, Hariprasad CHANDRAKUMAR of Beaverton OR (US) for intel corporation, Georgios DOGIAMIS of Chandler AZ (US) for intel corporation, Benjamin HERSHBERG of Portland OR (US) for intel corporation
IPC Code(s): H03M1/46, H03M1/12
CPC Code(s): H03M1/462
Abstract: disclosed herein are devices, methods, and systems related to analog-to-digital converters (adcs), and in particular, to settling the reference voltage in an adc and to settling the reference voltage in a time-interleaved arrangement of adcs. a method of settling of a reference voltage in an adc may include generating, on a reference voltage line, an analog reference voltage, and connecting, at the time of generating the analog reference voltage, a pre-charged capacitor of the adc to the reference voltage line to reduce a voltage error during the generation of the analog reference voltage.
20250030636. RULE LOOKUP FOR PROCESSING PACKETS_simplified_abstract_(intel corporation)
Inventor(s): Doron NAKAR of Shoham (IL) for intel corporation, Anurag AGRAWAL of Santa Clara CA (US) for intel corporation
IPC Code(s): H04L45/748, H04L45/42
CPC Code(s): H04L45/748
Abstract: examples described herein relate to configuring a device to perform longest prefix match (lpm) of rules associated with nodes to identify an action to perform on a packet. the rules can be stored among a memory and ternary content-addressable memory (tcam) based on available memory capacity of the tcam.
Inventor(s): Cheng-Ying Huang of Hillsboro OR (US) for intel corporation, Ashish Agrawal of Hillsboro OR (US) for intel corporation, Gilbert Dewey of Beaverton OR (US) for intel corporation, Abhishek A. Sharma of Hillsboro OR (US) for intel corporation, Wilfred Gomes of Portland OR (US) for intel corporation, Jack Kavalieros of Portland OR (US) for intel corporation
IPC Code(s): H10B12/00, H01L21/683, H01L29/06, H01L29/423, H01L29/66, H01L29/786, H10B53/30
CPC Code(s): H10B12/30
Abstract: monolithic two-dimensional (2d) arrays of double-sided dram cells including a frontside bit cell over a backside bit cell. each double-sided cell includes a stacked transistor structure having at least a first transistor over a second transistor. each double-sided cell further includes a first capacitor on a frontside of the stacked transistor structure and electrically coupled to a source/drain of the first transistor. each double-sided cell further includes a second capacitor on a backside of the stacked transistor structure and electrically coupled to a source/drain of the second transistor. frontside cell addressing interconnects are electrically coupled to other terminals of at least the first transistor while one or more backside addressing interconnects are electrically coupled to at least one terminal of the second transistor or second capacitor.
Inventor(s): Walid M. HAFEZ of Portland OR (US) for intel corporation, Jeng-Ya D. YEH of Portland OR (US) for intel corporation, Curtis TSAI of Beaverton OR (US) for intel corporation, Joodong PARK of Portland OR (US) for intel corporation, Chia-Hong JAN of Portland OR (US) for intel corporation, Gopinath BHIMARASETTI of Portland OR (US) for intel corporation
IPC Code(s): H01L27/12, H01L21/02, H01L21/28, H01L21/8234, H01L21/84, H01L29/423, H01L29/51, H01L29/66
CPC Code(s): H01L27/1211
Abstract: high voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. for example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. a first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. the first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. the first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. the semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. the second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. the second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.
Inventor(s): Shigeki TOMISHIMA of Portland OR (US) for intel corporation
IPC Code(s): H01L27/12, H01L21/02, H01L21/4763, H01L29/24, H01L29/66, H01L29/786
CPC Code(s): H01L27/1225
Abstract: an example two transistor (2t) gain cell memory with indium-gallium-zinc-oxide (igzo) transistors. examples include igzo transistors included in a dynamic random access memory (dram) cell. the igzo transistors included in the dram cell are described as being formed or created in a back end (be) metal process stack of an integrated circuit chip or die.
- Intel Corporation
- G06F3/06
- G06F13/16
- G06F13/40
- G06F21/78
- G06F21/79
- G06F21/85
- CPC G06F3/0622
- Intel corporation
- G06F9/30
- CPC G06F9/30054
- CPC G06F9/30145
- G06F9/50
- G06F7/50
- G06F9/48
- G06F15/80
- G06F15/82
- G06N20/00
- CPC G06F9/5027
- G06F12/128
- G06F12/084
- G06F12/0895
- G06N3/044
- G06N3/045
- G06N3/063
- G06N3/084
- CPC G06F12/128
- G06F15/78
- G06F7/544
- G06F7/575
- G06F7/58
- G06F9/38
- G06F12/02
- G06F12/06
- G06F12/0802
- G06F12/0804
- G06F12/0811
- G06F12/0862
- G06F12/0866
- G06F12/0871
- G06F12/0875
- G06F12/0882
- G06F12/0888
- G06F12/0891
- G06F12/0893
- G06F12/0897
- G06F12/1009
- G06F17/16
- G06F17/18
- G06N3/08
- G06T1/20
- G06T1/60
- G06T15/06
- H03M7/46
- CPC G06F15/7839
- G06N3/082
- CPC G06N3/082
- G06T15/00
- G06T3/4053
- G06T15/50
- CPC G06T15/005
- H01L23/48
- H01L27/092
- H01L29/06
- H01L29/423
- H01L29/78
- CPC H01L23/481
- H01L23/498
- H01L21/66
- H01L23/00
- H01L23/544
- H01L23/58
- H01L25/065
- H01L25/18
- CPC H01L23/49827
- H01L23/522
- G06F1/16
- H01L21/768
- H01L23/14
- H01L23/50
- H01L23/528
- CPC H01L23/5222
- H01L23/535
- H01L21/28
- H01L21/8234
- H01L23/485
- H01L23/532
- H01L27/088
- H01L29/08
- H01L29/417
- H01L29/49
- H01L29/66
- CPC H01L23/535
- H01L23/538
- H01L21/48
- H01L21/56
- H01L21/683
- H01L23/31
- H01L23/367
- H01L25/00
- CPC H01L23/5381
- H03M1/46
- H03M1/12
- CPC H03M1/462
- H04L45/748
- H04L45/42
- CPC H04L45/748
- H10B12/00
- H01L29/786
- H10B53/30
- CPC H10B12/30
- H01L27/12
- H01L21/02
- H01L21/84
- H01L29/51
- CPC H01L27/1211
- H01L21/4763
- H01L29/24
- CPC H01L27/1225
