Intel Corporation patent applications on March 27th, 2025
Patent Applications by Intel Corporation on March 27th, 2025
Intel Corporation: 88 patent applications
Intel Corporation has applied for patents in the areas of H01L23/00 (14), H01L23/498 (11), H01L29/66 (9), H01L29/06 (8), H01L25/065 (8) G06F15/7839 (3), H10D62/121 (2), G06F12/1408 (2), H10B80/00 (2), G06T1/20 (2)
With keywords such as: layer, memory, substrate, circuit, structure, include, device, source, data, and embodiment in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): Sergei Sochava of Sunnyvale CA US for intel corporation
IPC Code(s): G01S7/481, G01S7/4911, H01S5/068
CPC Code(s): G01S7/4815
Abstract: technologies for tunable lasers in a photonic integrated circuit (pic) die are disclosed. in an illustrative embodiment, a lidar system includes a pic die with two lasers. the pic die includes a switch to switch between the output of the first laser and the output of the second laser. each laser can be tuned to different peaks of a bragg grating in the cavity of the laser, and each laser can be frequency swept within the peak of the bragg grating. in operation, one laser is changed to a different peak of the bragg grating and allowed to stabilize while the other laser is selected for output and frequency swept. in this manner, one laser stabilizes while the other one is used. such a lidar system can implement frequency-modulated continuous-wave (fmcw) lidar with a stable, compact laser source.
20250102740. V-GROOVE FIBER STOP_simplified_abstract_(intel corporation)
Inventor(s): Harel FRISH of Albuquerque NM US for intel corporation, Hari MAHALINGAM of San Jose CA US for intel corporation, Saeed FATHOLOLOUMI of Los Gatos CA US for intel corporation, Shane YERKES of Placitas NM US for intel corporation, John HECK of Berkeley CA US for intel corporation, Wei QIAN of Walnut CA US for intel corporation
IPC Code(s): G02B6/36
CPC Code(s): G02B6/3636
Abstract: a device comprising a silicon substrate and a waveguide on the silicon substrate. a groove is in the substrate, the groove having a sloped rear wall adjacent to the waveguide. a trench is in the substrate, the trench along a second direction generally orthogonal to the first direction across the sloped rear wall, the trench having a vertical wall at an intersection with the sloped rear wall. an optical fiber in the groove with one end of the optical fiber abutting the vertical wall.
20250102744. TECHNOLOGIES FOR FIBER ARRAY UNIT LID DESIGNS_simplified_abstract_(intel corporation)
Inventor(s): Feifei Cheng of Chandler AZ US for intel corporation, Kumar Abhishek Singh of Phoenix AZ US for intel corporation, Peter A. Williams of Phoenix AZ US for intel corporation, Ziyin Lin of Chandler AZ US for intel corporation, Fan Fan of Chandler AZ US for intel corporation, Yang Wu of Chandler AZ US for intel corporation, Saikumar Jayaraman of Chandler AZ US for intel corporation, Baris Bicen of Chandler AZ US for intel corporation, Darren Vance of Gilbert AZ US for intel corporation, Anurag Tripathi of Gilbert AZ US for intel corporation, Divya Pratap of Hillsboro OR US for intel corporation, Stephanie J. Arouh of Phoenix AZ US for intel corporation
IPC Code(s): G02B6/42
CPC Code(s): G02B6/423
Abstract: technologies for fiber array unit (fau) lid designs are disclosed. in one embodiment, channels in the lid allow for suction to be applied to fibers that the lid covers, pulling the fibers into place in a v-groove. the suction can hold the fibers in place as the fiber array unit is mated with a photonic integrated circuit (pic) die. additionally or alternatively, channels can be on pitch, allowing for pulling the fau towards a pic die as well as sensing the position and alignment of the fau to the pic die. in another embodiment, a warpage amount of a pic die is characterized, and a fau lid with a similar warpage is fabricated, allowing for the fau to position fibers correctly relative to waveguides in the pic die. in another embodiment, a fau has an extended lid, which can provide fiber protection as well as position and parallelism tolerance control.
20250102745. ROBUST WAVEGUIDE ALIGNMENT MECHANISM_simplified_abstract_(intel corporation)
Inventor(s): Mohanraj Prabhugoud of Portland OR US for intel corporation, David Shia of Portland OR US for intel corporation, Hari Mahalingam of San Jose CA US for intel corporation, John M. Heck of Berkeley CA US for intel corporation, John Robert Macdonald of Linlithgow GB for intel corporation, Duncan Peter Dore of Glasgow GB for intel corporation, Eric J. M. Moret of Beaverton OR US for intel corporation, Nicholas D. Psaila of Lanark GB for intel corporation, Sang Yup Kim of Sunnyvale CA US for intel corporation, Shane Kevin Yerkes of Placitas NM US for intel corporation, Harel Frish of Albuquerque NM US for intel corporation
IPC Code(s): G02B6/42
CPC Code(s): G02B6/4231
Abstract: in one embodiment, a device includes a fiber array unit (fau) coupled to a photonics integrated circuit (pic) die. the pic die includes a cavity defined at an edge of the pic die, with outer edges of the cavity being formed at an angle less than 90 degrees with respect to a bottom surface of the cavity. the pic die further includes first waveguides protruding into the cavity of the pic die. the fau includes a shelf portion extending from a body portion, and a plurality of second waveguides protruding from an outer edge of the shelf portion opposite the body portion. the fau further includes alignment structures on outer edges of the shelf portion that are in contact with the angled edges of the cavity of the pic die.
20250102903. EUV MASK AND PELLICLE ASSEMBLY_simplified_abstract_(intel corporation)
Inventor(s): Yongbae KIM of San Jose CA US for intel corporation
IPC Code(s): G03F1/64, G03F1/22
CPC Code(s): G03F1/64
Abstract: provided is a pellicle assembly that is sufficiently conductive in cooperation with a photomask that is mounted to the pellicle assembly to protect the pellicle and mask from electro static discharge.
Inventor(s): Harish K. Krishnamurthy of Beaverton OR US for intel corporation, Nicolas Butzen of Portland OR US for intel corporation, Khondker Ahmed of Hillsboro OR US for intel corporation, Nachiket Desai of Portland OR US for intel corporation, Su Hwan Kim of Portland OR US for intel corporation, Krishnan Ravichandran of Saratoga CA US for intel corporation, Kaladhar Radhakrishnan of Chandler AZ US for intel corporation, Jonathan Douglas of Cave Creek AZ US for intel corporation
IPC Code(s): G05F1/56
CPC Code(s): G05F1/56
Abstract: embodiments herein relate to a voltage regular (vr) formed from dies stacked on a package base layer. the vr can include a first part on a first die and a second part on a second die, where the different parts are selected based on characteristics of the respective die such as their voltage domains or technologies. in a capacitor-based vr, an input capacitor and switches subject to a relatively high input voltage can be provided in the first die, while a flying capacitor, output capacitor and switches subject to a relatively low output voltage can be provided in the second die. in an inductor-based vr, an inductor and one or more switches subject to a relatively high input voltage can be provided in the first die, while an output capacitor subject to a relatively low output voltage can be provided in the second die.
Inventor(s): Khondker Ahmed of Hillsboro OR US for intel corporation, Nicolas Butzen of Portland OR US for intel corporation, Nachiket Desai of Portland OR US for intel corporation, Su Hwan Kim of Portland OR US for intel corporation, Harish K. Krishnamurthy of Beaverton OR US for intel corporation, Krishnan Ravichandran of Saratoga CA US for intel corporation, Kaladhar Radhakrishnan of Chandler AZ US for intel corporation, Jonathan Douglas of Cave Creek AZ US for intel corporation
IPC Code(s): G05F1/56
CPC Code(s): G05F1/56
Abstract: embodiments herein relate to a stacked semiconductor structure which includes a first voltage regulator (vr), external to a package, for supplying current to a compute die in the package. when the required current exceeds a threshold, an additional current source is activated. the additional current source can include a second vr, also external to the package, for supplying current to an integrated voltage regulator (ivr) in the package. the ivr performs voltage down conversion and current multiplication to output a portion of the required current above the threshold, while the output of the first vr is capped at the threshold.
Inventor(s): Sarang Akotkar of Bangalore IN for intel corporation, Guneshwor Singh of Bangalore IN for intel corporation
IPC Code(s): G06F9/30
CPC Code(s): G06F9/30014
Abstract: systems, apparatuses and methods may provide for technology that conducts a first split of a first floating point (fp) number into a first part and a second part, conducts a second split of a second fp number into a third part and a fourth part, conducts a first reduction sum operation between the first part and the third part to obtain a first intermediate result, and conducts a second reduction sum operation between the second part and the fourth part to obtain a second intermediate result.
20250103331. PROCESSOR EMBEDDED STREAMING BUFFER_simplified_abstract_(intel corporation)
Inventor(s): Joseph Williams of Holmdel NJ US for intel corporation
IPC Code(s): G06F9/30, G06F9/355, G06F9/38, G06F15/78
CPC Code(s): G06F9/30036
Abstract: techniques are disclosed for the use of local buffers integrated into the execution units of an array processor architecture. the use of local buffers results in less communication across the interconnection network implemented by processors, and increases interconnection network bandwidth, increases the speed of computations, and decreases power usage.
20250103337. APPARATUS AND METHOD FOR PARTITIONED SHUFFLES_simplified_abstract_(intel corporation)
Inventor(s): Simon PENNYCOOK of San Jose CA US for intel corporation, Christopher J. HUGHES of Santa Clara CA US for intel corporation
IPC Code(s): G06F9/30
CPC Code(s): G06F9/30167
Abstract: an apparatus and method for partitioned shuffling of data elements. a first partition is associated with a first number of source data elements corresponding to a first plurality of lanes having a first plurality of lane identifiers (ids) and a second partition is associated with a second number of source data elements corresponding to a second plurality of lanes having a second plurality of lane ids. a bounded offset vector is generated based on allowable ranges for a plurality of offset values associated with the source data elements. an index vector is generated by permuting the first and second plurality of lane ids in accordance with the bounded offset vector.
Inventor(s): Christopher J. HUGHES of Santa Clara CA US for intel corporation, Prasoonkumar SURTI of Folsom CA US for intel corporation, Guei-Yuan LUEH of San Jose CA US for intel corporation, Adam T. LAKE of Portland OR US for intel corporation, Jill BOYCE of Portland OR US for intel corporation, Subramaniam MAIYURAN of Gold River CA US for intel corporation, Lidong XU of BEIJING CN for intel corporation, James M. HOLLAND of Folsom CA US for intel corporation, Vasanth RANGANATHAN of El Dorado Hills CA US for intel corporation, Nikos KABURLASOS of Folsom CA US for intel corporation, Altug KOKER of El Dorado Hills CA US for intel corporation, Abhishek R. Appu of El Dorado Hills CA US for intel corporation
IPC Code(s): G06F9/38, G06F9/50, G06F9/54, G06F12/084, G06T1/60
CPC Code(s): G06F9/3891
Abstract: embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. other embodiments may be described and claimed.
Inventor(s): Ming WU of Shanghai CN for intel corporation, Addicam V SANJAY of Gilbert AZ US for intel corporation, Fujin HUANG of Shanghai CN for intel corporation
IPC Code(s): G06F9/4401
CPC Code(s): G06F9/4406
Abstract: it is provided an apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions. the machine-readable instructions comprise instructions to obtain a first data structure, the first data structure indicating which data block of a block-based core system image is available in a local storage circuitry. the machine-readable instructions further comprise instructions to check, during loading of at least one component of a software, if a data block required during execution of the software is available in the local storage circuitry according to the first data structure. the machine-readable instructions further comprise instructions to obtain the data block from a server if the required data block is not available, wherein the server is storing a copy of the core system image.
20250103380. VIRTUALIZATION OF DEVICE INTERFACES_simplified_abstract_(intel corporation)
Inventor(s): Kasper WSZOLEK of Gdansk PL for intel corporation, Janusz JURSKI of Beaverton OR US for intel corporation, Mariusz ORIOL of Gdynia PL for intel corporation, Matthew James ADILETTA of Bolton MA US for intel corporation
IPC Code(s): G06F9/455, G06F13/38, G06F13/42
CPC Code(s): G06F9/45558
Abstract: examples described herein relate to at least one processor that is to communicate with a management controller to communicate with multiple interfaces. in some examples, wherein at least two of the multiple interfaces are to provide boot firmware code to the at least one processor and a connection interface.
Inventor(s): Andrew J. Herdrich of Hillsboro OR US for intel corporation, Daniel Joe of Sacramento CA US for intel corporation, Filip Schmole of Portland OR US for intel corporation, Philip Abraham of Beaverton OR US for intel corporation, Stephen R. Van Doren of Portland OR US for intel corporation, Priya Autee of Chandler AZ US for intel corporation, Rajesh M. Sankaran of Portland OR US for intel corporation, Anthony Luck of San Jose CA US for intel corporation, Philip Lantz of Cornelius OR US for intel corporation, Eric Wehage of Tenino WA US for intel corporation, Edwin Verplanke of Chandler AZ US for intel corporation, James Coleman of Mesa AZ US for intel corporation, Scott Oehrlein of Gilbert AZ US for intel corporation, David M. Lee of Portland OR US for intel corporation, Lee Albion of Coeur d'Alene ID US for intel corporation, David Harriman of Portland OR US for intel corporation, Vinit Mathew Abraham of Hillsboro OR US for intel corporation, Yi-Feng Liu of Chandler AZ US for intel corporation, Manjula Peddireddy of Santa Clara CA US for intel corporation, Robert G. Blankenship of Tacoma WA US for intel corporation
IPC Code(s): G06F9/50
CPC Code(s): G06F9/5055
Abstract: techniques for quality of service (qos) support for input/output devices and other agents are described. in embodiments, a processing device includes execution circuitry to execute a plurality of software threads; hardware to control monitoring or allocating, among the plurality of software threads, one or more shared resources; and configuration storage to enable the monitoring or allocating of the one or more shared resources among the plurality of software threads and one or more channels through which one or more devices are to be connected to the one or more shared resources.
Inventor(s): SERGEJ DEUTSCH of Hillsboro OR US for intel corporation, KARANVIR GREWAL of Hillsboro OR US for intel corporation, DAVID M. DURHAM of Hillsboro, OR, 97123 OR US for intel corporation
IPC Code(s): G06F11/10, G06F21/64
CPC Code(s): G06F11/1064
Abstract: an apparatus and method for efficient encoding for trusted environments including full error correction. one embodiment of a processor comprises: a plurality of cores to execute instructions;
Inventor(s): SERGEJ DEUTSCH of Hillsboro OR US for intel corporation, KARANVIR GREWAL of Hillsboro OR US for intel corporation, DAVID M. DURHAM of Hillsboro, OR, 97123 OR US for intel corporation
IPC Code(s): G06F11/10, G06F21/64
CPC Code(s): G06F11/1064
Abstract: a memory controller coupled to the plurality of cores, the memory controller operable in a first error correction mode and a second error correction mode, the memory controller comprising: a decoder to decode first error correction code (ecc) bits encoded in accordance with the first error correction mode to determine a first syndrome and a second syndrome based on data corresponding to the ecc bits; error detection circuitry to determine whether one or both of the first syndrome and the second syndrome indicates an error in the data; and an encoder to generate second ecc bits in accordance with the second error correction mode, the ecc bits to be encoded based on whether one or both of the first syndrome and the second syndrome indicates an error.
Inventor(s): Vasanth Ranganathan of El Dorado Hills CA US for intel corporation, Joydeep Ray of Folsom CA US for intel corporation, Abhishek R. Appu of El Dorado Hills CA US for intel corporation, Nikos Kaburlasos of Folsom CA US for intel corporation, Lidong Xu of Beijing CN for intel corporation, Subramaniam Maiyuran of Gold River CA US for intel corporation, Altug Koker of El Dorado Hills CA US for intel corporation, Naveen Matam of Rancho Cordova CA US for intel corporation, James Holland of Folsom CA US for intel corporation, Brent Insko of Portland OR US for intel corporation, Sanjeev Jahagirdar of Folsom CA US for intel corporation, Scott Janus of Loomis CA US for intel corporation, Durgaprasad Bilagi of Folsom CA US for intel corporation, Xinmin Tian of Union City CA US for intel corporation
IPC Code(s): G06F11/10, G06F12/0802, G06T1/20, G06T1/60
CPC Code(s): G06F11/1068
Abstract: apparatuses including a graphics processing unit, graphics multiprocessor, or graphics processor having an error detection correction logic for cache memory or shared memory are disclosed. in one embodiment, a graphics multiprocessor includes cache or local memory for storing data and error detection correction circuitry integrated with or coupled to the cache or local memory. the error detection correction circuitry is configured to perform a tag read for data of the cache or local memory to check error detection correction information.
Inventor(s): Ramya Prabhu of Bengaluru IN for intel corporation, Joydeep Rakshit of Bengaluru IN for intel corporation, Anant Vithal Nori of Bengaluru IN for intel corporation, Stanislav Shwartsman of Haifa IL for intel corporation
IPC Code(s): G06F12/1027, G06F12/02, G06F12/121
CPC Code(s): G06F12/1027
Abstract: techniques for victim buffering through translation lookaside buffer (tlb) partitioning are described. in certain examples, a system includes a memory; an execution circuitry to generate a memory access request for a virtual memory address of the memory; a first level translation lookaside buffer to store virtual address to physical address mappings; a victim translation lookaside buffer to store a virtual address to physical address mapping evicted from the first level translation lookaside buffer; a second level translation lookaside buffer; and a cache coherency circuitry to search the first level translation lookaside buffer and the victim translation lookaside buffer for a corresponding physical address mapped to the virtual memory address for the memory access request, and for a miss in the first level translation lookaside buffer and the victim translation lookaside buffer, search the second level translation lookaside buffer for the corresponding physical address mapped to the virtual memory address for the memory access request, and for a hit in the victim translation lookaside buffer, provide the corresponding physical address mapped to the virtual memory address for the memory access request.
20250103511. SYSTEMS AND METHODS FOR CACHE OPTIMIZATION_simplified_abstract_(intel corporation)
Inventor(s): Altug Koker of El Dorado Hills CA US for intel corporation, Joydeep Ray of Folsom CA US for intel corporation, Elmoustapha Ould-Ahmed-Vall of Chandler AZ US for intel corporation, Abhishek Appu of El Dorado Hills CA US for intel corporation, Aravindh Anantaraman of Folsom CA US for intel corporation, Valentin Andrei of San Jose CA US for intel corporation, Durgaprasad Bilagi of Folsom CA US for intel corporation, Varghese George of Folsom CA US for intel corporation, Brent Insko of Portland OR US for intel corporation, Sanjeev Jahagirdar of Folsom CA US for intel corporation, Scott Janus of Loomis CA US for intel corporation, Pattabhiraman K of Bangalore IN for intel corporation, SungYe Kim of Folsom CA US for intel corporation, Subramaniam Maiyuran of Gold River CA US for intel corporation, Vasanth Ranganathan of El Dorado Hills CA US for intel corporation, Lakshminarayanan Striramassarma of Folsom CA US for intel corporation, Xinmin Tian of Union City CA US for intel corporation
IPC Code(s): G06F12/123, G06F12/0875, G06F12/0891, G06T1/60
CPC Code(s): G06F12/123
Abstract: systems and methods for improving cache efficiency and utilization are disclosed. in one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. the cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received.
Inventor(s): Thomas Unterluggauer of Villach AT for intel corporation, Fangfei Liu of Hillsboro OR US for intel corporation, Scott D. Constable of Portland OR US for intel corporation, Carlos V. Rozas of Portland OR US for intel corporation, Gilles Pokam of Livermore CA US for intel corporation, Boris Dolgunov of San Jose CA US for intel corporation
IPC Code(s): G06F12/14, G06F12/0808
CPC Code(s): G06F12/1408
Abstract: techniques for cache scrubbing for cache-set randomization to resist contention-based cache attacks are described. in certain examples, a system includes a memory; an execution circuit to cause a memory access request for the memory; a cache to store a plurality of sets that each include a plurality of cache lines from the memory; a cache randomizer circuit to generate a randomized index into the plurality of sets of the cache based on an address of the memory access request; and a cache scrubber circuit to determine that a number of invalid cache lines in a set of the plurality of sets of the cache is less than a threshold number of invalid cache lines, and in response, invalidate a valid cache line in the set of the plurality of sets of the cache.
Inventor(s): Reshma Lal of Portland OR US for intel corporation, Pradeep M. Pappachan of Tualatin OR US for intel corporation, Luis Kida of Beaverton OR US for intel corporation, Krystof Zmudzinski of Forest Grove OR US for intel corporation, Siddhartha Chhabra of Portland OR US for intel corporation, Abhishek Basak of Bothell WA US for intel corporation, Alpa Narendra Trivedi of Portland OR US for intel corporation, Anna Trikalinou of Hillsboro OR US for intel corporation, David M. Lee of Portland OR US for intel corporation, Vedvyas Shanbhogue of Austin TX US for intel corporation, Utkarsh Y. Kakaiya of El Dorado Hills CA US for intel corporation
IPC Code(s): G06F12/14, G06F9/38, G06F9/455, G06F12/0802, G06F21/57, G06F21/60, G06F21/64, G06F21/76, G06F21/79, H04L9/06, H04L9/08, H04L9/32, H04L41/046, H04L41/28
CPC Code(s): G06F12/1408
Abstract: technologies for secure device configuration and management include a computing device having an i/o device. a trusted agent of the computing device is trusted by a virtual machine monitor of the computing device. the trusted agent securely commands the i/o device to enter a trusted i/o mode, securely commands the i/o device to set a global lock on configuration registers, receives configuration data from the i/o device, and provides the configuration data to a trusted execution environment. in the trusted i/o mode, the i/o device rejects a configuration command if a configuration register associated with the configuration command is locked and the configuration command is not received from the trusted agent. the trusted agent may provide attestation information to the trusted execution environment. the trusted execution environment may verify the configuration data and the attestation information. other embodiments are described and claimed.
Inventor(s): JUNYUAN WANG of Shanghai CN for intel corporation, JOHN J BROWNE of Limerick GB for intel corporation, MAKSIM LUKOSHKOV of Clarecastle IE for intel corporation, XIN ZENG of Shanghai CN for intel corporation, TOMASZ KANTECKI of Ennis, Co.Clare IE for intel corporation, WEIGANG LI of Shanghai CN for intel corporation, WENQIAN YU of Shanghai CN for intel corporation
IPC Code(s): G06F13/16, G06F13/42
CPC Code(s): G06F13/16
Abstract: apparatuses, methods, and computer readable media for regulating command submission to a shared device. a processor may receive a command for an operation to be performed by another device. the processor may determine an identifier of an address space of a process associated with the command. the processor may determine whether to accept or reject the command.
Inventor(s): Kannappan Rajaraman of Bangalore IN for intel corporation, Udaya Natarajan of El Dorado Hills CA US for intel corporation
IPC Code(s): G06F13/42
CPC Code(s): G06F13/4282
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed. an example apparatus includes a usb-c port; power delivery circuitry to determine, based on a mode-support message accessed via the usb-c port, that an external device supports compute express link (cxl) as a standalone protocol over usb-c; and multiplexer management circuitry to cause the power delivery circuitry to transmit a cxl status message to the external device via the usb-c port.
20250103546. CACHE STRUCTURE AND UTILIZATION_simplified_abstract_(intel corporation)
Inventor(s): Altug Koker of El Dorado Hills CA US for intel corporation, Lakshminarayanan Striramassarma of Folsom CA US for intel corporation, Aravindh Anantaraman of Folsom CA US for intel corporation, Valentin Andrei of San Jose CA US for intel corporation, Abhishek R. Appu of El Dorado Hills CA US for intel corporation, Sean Coleman of Folsom CA US for intel corporation, Varghese George of Folsom CA US for intel corporation, Pattabhiraman K of Bangalore KA IN for intel corporation, Mike MacPherson of Portland OR US for intel corporation, Subramaniam Maiyuran of Gold River CA US for intel corporation, ElMoustapha Ould-Ahmed-Vall of Chandler AZ US for intel corporation, Vasanth Ranganathan of El Dorado Hills CA US for intel corporation, Joydeep Ray of Folsom CA US for intel corporation, Jayakrishna P S of Bangalore KA IN for intel corporation, Prasoonkumar Surti of Folsom CA US for intel corporation
IPC Code(s): G06F15/78, G06F7/544, G06F7/575, G06F7/58, G06F9/30, G06F9/38, G06F9/50, G06F12/02, G06F12/06, G06F12/0802, G06F12/0804, G06F12/0811, G06F12/0862, G06F12/0866, G06F12/0871, G06F12/0875, G06F12/0882, G06F12/0888, G06F12/0891, G06F12/0893, G06F12/0895, G06F12/0897, G06F12/1009, G06F12/128, G06F15/80, G06F17/16, G06F17/18, G06N3/08, G06T1/20, G06T1/60, H03M7/46
CPC Code(s): G06F15/7839
Abstract: embodiments are generally directed to cache structure and utilization. an embodiment of an apparatus includes one or more processors including a graphics processor; a memory for storage of data for processing by the one or more processors; and a cache to cache data from the memory; wherein the apparatus is to provide for dynamic overfetching of cache lines for the cache, including receiving a read request and accessing the cache for the requested data, and upon a miss in the cache, overfetching data from memory or a higher level cache in addition to fetching the requested data, wherein the overfetching of data is based at least in part on a current overfetch boundary, and provides for data is to be prefetched extending to the current overfetch boundary.
Inventor(s): Prasoonkumar Surti of Folsom CA US for intel corporation, Subramaniam Maiyuran of Gold River CA US for intel corporation, Valentin Andrei of San Jose CA US for intel corporation, Abhishek Appu of El Dorado Hills CA US for intel corporation, Varghese George of Folsom CA US for intel corporation, Altug Koker of El Dorado Hills CA US for intel corporation, Mike Macpherson of Portland OR US for intel corporation, Elmoustapha Ould-Ahmed-Vall of Chandler AZ US for intel corporation, Vasanth Ranganathan of El Dorado Hills CA US for intel corporation, Joydeep Ray of Folsom CA US for intel corporation, Lakshminarayanan Striramassarma of Folsom CA US for intel corporation, SungYe Kim of Folsom CA US for intel corporation
IPC Code(s): G06F15/78, G06F7/544, G06F7/575, G06F7/58, G06F9/30, G06F9/38, G06F9/50, G06F12/02, G06F12/06, G06F12/0802, G06F12/0804, G06F12/0811, G06F12/0862, G06F12/0866, G06F12/0871, G06F12/0875, G06F12/0882, G06F12/0888, G06F12/0891, G06F12/0893, G06F12/0895, G06F12/0897, G06F12/1009, G06F12/128, G06F15/80, G06F17/16, G06F17/18, G06N3/08, G06T1/20, G06T1/60, H03M7/46
CPC Code(s): G06F15/7839
Abstract: embodiments described herein include software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. one embodiment provides techniques to optimize training and inference on a systolic array when using sparse data. one embodiment provides techniques to use decompression information when performing sparse compute operations. one embodiment enables the disaggregation of special function compute arrays via a shared reg file. one embodiment enables packed data compress and expand operations on a gpgpu. one embodiment provides techniques to exploit block sparsity within the cache hierarchy of a gpgpu.
Inventor(s): Altug Koker of El Dorado Hills CA US for intel corporation, Joydeep Ray of Folsom CA US for intel corporation, Ben Ashbaugh of Folsom CA US for intel corporation, Jonathan Pearce of Hillsboro OR US for intel corporation, Abhishek Appu of El Dorado Hills CA US for intel corporation, Vasanth Ranganathan of El Dorado Hills CA US for intel corporation, Lakshminarayanan Striramassarma of Folsom CA US for intel corporation, Elmoustapha Ould-Ahmed-Vall of Chandler AZ US for intel corporation, Aravindh Anantaraman of Folsom CA US for intel corporation, Valentin Andrei of San Jose CA US for intel corporation, Nicolas Galoppo Von Borries of Portland OR US for intel corporation, Varghese George of Folsom CA US for intel corporation, Yoav Harel of Carmichael CA US for intel corporation, Arthur Hunter, JR. of Cameron Park CA US for intel corporation, Brent Insko of Portland OR US for intel corporation, Scott Janus of Loomis CA US for intel corporation, Pattabhiraman K of Bangalore IN for intel corporation, Mike Macpherson of Portland OR US for intel corporation, Subramaniam Maiyuran of Gold River CA US for intel corporation, Marian Alin Petre of San Mateo CA US for intel corporation, Murali Ramadoss of Folsom CA US for intel corporation, Shailesh Shah of Folsom CA US for intel corporation, Kamal Sinha of Folsom CA US for intel corporation, Prasoonkumar Surti of Folsom CA US for intel corporation, Vikranth Vemulapalli of Folsom CA US for intel corporation
IPC Code(s): G06F15/78, G06F7/544, G06F7/575, G06F7/58, G06F9/30, G06F9/38, G06F9/50, G06F12/02, G06F12/06, G06F12/0802, G06F12/0804, G06F12/0811, G06F12/0862, G06F12/0866, G06F12/0871, G06F12/0875, G06F12/0882, G06F12/0888, G06F12/0891, G06F12/0893, G06F12/0895, G06F12/0897, G06F12/1009, G06F12/128, G06F15/80, G06F17/16, G06F17/18, G06N3/08, G06T1/20, G06T1/60, G06T15/06, H03M7/46
CPC Code(s): G06F15/7839
Abstract: systems and methods for improving cache efficiency and utilization are disclosed. in one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. the cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.
Inventor(s): Karthik Kumar of Chandler AZ US for intel corporation, Marcos Carranza of Portland OR US for intel corporation, Thomas Willhalm of Sandhausen DE for intel corporation, Patrick Connor of Beaverton OR US for intel corporation
IPC Code(s): G06N20/00, G06F16/334
CPC Code(s): G06N20/00
Abstract: an apparatus includes a host interface, a network interface, and programmable circuitry communicably coupled to the host interface and the network interface, the programmable circuitry comprising one or more processors are to implement network interface functionality and are to receive a prompt directed to an artificial intelligence (ai) model hosted by a host device communicably coupled to the host interface, apply a prompt tuning model to the prompt to generate an initial augmented prompt, compare the initial augmented prompt for a match with stored data of a prompt augmentation tracking table comprising real-time datacenter trend data and cross-network historical augmentation data from programmable network interface devices in a datacenter hosting the apparatus, generate, in response to identification of the match with the stored data, a final augmented prompt based on the match, and transmit the final augmented prompt to the ai model.
Inventor(s): Altug Koker of El Dorado Hills CA US for intel corporation, Lance Cheney of El Dorado Hills CA US for intel corporation, Eric Finley of Ione CA US for intel corporation, Varghese George of Folsom CA US for intel corporation, Sanjeev Jahagirdar of Folsom CA US for intel corporation, Josh Mastronarde of Sacramento CA US for intel corporation, Naveen Matam of Rancho Cordova CA US for intel corporation, Iqbal Rajwani of Roseville CA US for intel corporation, Lakshminarayanan Striramassarma of Folsom CA US for intel corporation, Melaku Teshome of El Dorado Hills CA US for intel corporation, Vikranth Vemulapalli of Folsom CA US for intel corporation, Binoj Xavier of Folsom CA US for intel corporation
IPC Code(s): G06T1/20, G06F13/40
CPC Code(s): G06T1/20
Abstract: a disaggregated processor package can be configured to accept interchangeable chiplets. interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. chiplets from different ip designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. the fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the on-board logic of the chiplet. additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets. with such an interchangeable design, cache or dram memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.
Inventor(s): Abhishek Appu of El Dorado Hills CA US for intel corporation, Subramaniam Maiyuran of Gold River CA US for intel corporation, Mike Macpherson of Portland OR US for intel corporation, Fangwen Fu of Folsom CA US for intel corporation, Jiasheng Chen of El Dorado Hills CA US for intel corporation, Varghese George of Folsom CA US for intel corporation, Vasanth Ranganathan of El Dorado Hills CA US for intel corporation, Ashutosh Garg of Folsom CA US for intel corporation, Joydeep Ray of Folsom CA US for intel corporation
IPC Code(s): G06T1/20, G06F7/544, G06F9/30, G06F9/38, G06F9/50, G06F12/0806, G06F15/80, G06F17/16, G06N3/048, G06N3/08, G06N3/084
CPC Code(s): G06T1/20
Abstract: embodiments described herein include software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. one embodiment provides for data aware sparsity via compressed bitstreams. one embodiment provides for block sparse dot product instructions. one embodiment provides for a depth-wise adapter for a systolic array.
20250104326. PROGRESSIVE MULTISAMPLE ANTI-ALIASING_simplified_abstract_(intel corporation)
Inventor(s): Abhishek R. Appu of El Dorado Hills CA US for intel corporation, Prasoonkumar Surti of Folsom CA US for intel corporation, Joydeep Ray of Folsom CA US for intel corporation, Michael J. Norris of Folsom CA US for intel corporation
IPC Code(s): G06T15/00, G06T11/40
CPC Code(s): G06T15/005
Abstract: one embodiment provides a graphics processor comprising an interface to a system interconnect and a graphics processor coupled to the interface, the graphics processor comprising circuitry configured to compact sample data for multiple sample locations of a pixel, map the multiple sample locations to memory locations that store compacted sample data, the memory locations in a memory of the graphics processor, apply lossless compression to the compacted sample data, and update a compression control surface associated with the memory locations, the compression control surface to specify a compression status for the memory locations
Inventor(s): Rafael ROSALES of Unterhaching DE for intel corporation, Ignacio J. ALVAREZ of Portland OR US for intel corporation, Michael PAULITSCH of Ottobrunn DE for intel corporation
IPC Code(s): G08G1/16, B60W50/16, G01S13/931, G06V20/58
CPC Code(s): G08G1/167
Abstract: a device for blind spot determination of a second vehicle in a vicinity of a first vehicle includes a processor, configured to determine one or more context variables associated with the second vehicle; modify a model of the second vehicle based on one or more context variables; and determine a probability of the first vehicle being within an area of limited visibility in the modified model.
20250104599. DISPLAY TIMING CONTROLLER AND METHOD_simplified_abstract_(intel corporation)
Inventor(s): Joy PODDAR of Bangalore IN for intel corporation, Dong-Ho HAN of Beaverton OR US for intel corporation, Pujitha DAVULURI of Portland OR US for intel corporation, Qing De XIA of Shanghai CN for intel corporation
IPC Code(s): G09G3/20
CPC Code(s): G09G3/2096
Abstract: a device includes a processor that is configured to determine a band used for wireless communication by a baseband modem; select an operational frequency for a display controller based on the determined band; and control the display controller to operate at the selected operational frequency.
Inventor(s): Kasper Wszolek of Gdansk PL for intel corporation, Atul Maheshwari of Portland OR US for intel corporation, Ankireddy Nalamalpu of Portland OR US for intel corporation, Siang Poh Loh of Sungai Petani MY for intel corporation
IPC Code(s): G11C7/10
CPC Code(s): G11C7/1063
Abstract: an integrated circuit includes a communication controller circuit for exchanging communications with a device external to the integrated circuit through a signal line, a current circuit coupled to the signal line, and a current controller circuit for causing the current circuit to provide a constant current to the signal line while a signal is transmitted through the signal line based on a command generated by the communication controller circuit.
Inventor(s): Abhishek A. Sharma of Portland OR US for intel corporation, Sagar Suthram of Portland OR US for intel corporation, Wilfred Gomes of Portland OR US for intel corporation, Anand S. Murthy of Portland OR US for intel corporation, Tahir Ghani of Portland OR US for intel corporation, Pushkar Sharad Ranade of San Jose CA US for intel corporation
IPC Code(s): G11C11/4091, G11C11/408, G11C11/4094
CPC Code(s): G11C11/4091
Abstract: an ic device may include memory layers over a logic layer. a memory layer includes memory arrays, each of which includes memory cells arranged in rows and columns. a row of memory cells may be associated with a word line. a column of memory cells may be associated with a bit line. bit lines of different memory arrays may be coupled using one or more vias or source/drain electrodes of transistors in the memory arrays. alternatively, word lines of different memory arrays may be coupled using one or more vias or gate electrodes of transistors in the memory arrays. the logic layer has a logic circuit that can control data read operations and data write operations of the memory layers. the logic layer may include a power interconnect, which facilitates power delivery to the memory layers, and a signal interconnect, which facilitates signal transmission within the memory device.
20250104797. MEMORY ISOLATION TO IMPROVE SYSTEM RELIABILITY_simplified_abstract_(intel corporation)
Inventor(s): Zhiguo Wei of Shanghai CN for intel corporation, Du Lin of Shanghai CN for intel corporation, Tao Xu of Shanghai CN for intel corporation, Yufu Li of Portland OR US for intel corporation, Zhenfu Chai of Shanghai CN for intel corporation
IPC Code(s): G11C29/00, G11C29/52
CPC Code(s): G11C29/76
Abstract: example systems, apparatus, articles of manufacture, and methods that perform memory preservation to improve system reliability are disclosed. example apparatus disclosed herein increment an error count after detection of an error associated with a memory cell. example apparatus also isolate a system memory address of the memory cell based on the error count.
Inventor(s): Jaeil Baek of Chandler AZ US for intel corporation, Brandon Christian Marin of Gilbert AZ US for intel corporation, Beomseok Choi of Chandler AZ US for intel corporation, Kaladhar Radhakrishnan of Chandler AZ US for intel corporation
IPC Code(s): H01F41/04, H01L23/498, H01L23/64
CPC Code(s): H01F41/046
Abstract: coaxial metal inductor loops and associated methods are disclosed. an example apparatus includes a substrate, first conductive material disposed along a first hole extending through the substrate, second conductive material disposed along a second hole extending through the substrate, and a magnetic material defining a continuous path completely encompassing both the first conductive material and the second conductive material in a plane perpendicular to an axis of the first hole.
Inventor(s): Yew San Lim of Gelugor MY for intel corporation, Ming-Sheng Tsai of Taipei TW for intel corporation, Chung Jen Ho of New Taipei City TW for intel corporation, Chi Chou Cheng of Taipei City TW for intel corporation, Min Suet Lim of Gelugor MY for intel corporation, Hari Raghavan Jayaraj of Bengaluru IN for intel corporation
IPC Code(s): H01H13/807, G06F1/16, H01H13/85, H01H13/86, H01H13/88
CPC Code(s): H01H13/807
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed for electronic devices with tactile keyboards. an example electronic device includes a tactile keyboard having a plurality of rows of keys; a printed circuit board; a first row of switches on the printed circuit board, a first row of the plurality of rows of keys to interact with the first row of switches; and a second row of switches on a component adjacent to the printed circuit board, a second row of the plurality of rows of keys to interact with the second row of switches.
Inventor(s): Thomas L. Sounart of Chandler AZ US for intel corporation, Adel Elsherbini of Chandler AZ US for intel corporation, Feras Eid of Chandler AZ US for intel corporation, Tushar Kanti Talukdar of Wilsonville OR US for intel corporation
IPC Code(s): H01L21/50, H01L21/78, H01L23/00
CPC Code(s): H01L21/50
Abstract: methods of selectively transferring portions of layers between substrates, and devices and systems formed using the same, are disclosed herein. in one embodiment, a first substrate with a release layer and a layer of integrated circuit (ic) components over the release layer is received, and a second substrate with one or more adhesive areas is received. the release layer on the first substrate is weakened. the first substrate is partially bonded to the second substrate, such that a subset of ic components on the first substrate are bonded to the adhesive areas on the second substrate. the first substrate is then separated from the second substrate, and the subset of ic components bonded to the second substrate are separated from the first substrate and remain on the second substrate.
20250105046. SELECTIVE LAYER TRANSFER_simplified_abstract_(intel corporation)
Inventor(s): Adel Elsherbini of Chandler AZ US for intel corporation, Thomas L. Sounart of Chandler AZ US for intel corporation, Feras Eid of Chandler AZ US for intel corporation, Tushar Kanti Talukdar of Wilsonville OR US for intel corporation, Brandon M. Rawlings of Chandler AZ US for intel corporation, Andrey Vyatskikh of Hillsboro OR US for intel corporation, Carlos Bedoya Arroyave of Portland OR US for intel corporation, Kimin Jun of Portland OR US for intel corporation, Shawna M. Liff of Scottsdale AZ US for intel corporation, Grant M. Kloster of Lake Oswego OR US for intel corporation, Richard F. Vreeland of Beaverton OR US for intel corporation, William P. Brezinski of Beaverton OR US for intel corporation, Johanna Swan of Scottsdale AZ US for intel corporation
IPC Code(s): H01L21/683, H01L23/00, H01L25/065
CPC Code(s): H01L21/6835
Abstract: methods of selectively transferring portions of layers between substrates, and devices and systems formed using the same, are disclosed herein. in one embodiment, a first substrate with a layer of integrated circuit (ic) components is received, and a second substrate with one or more adhesive areas is received. the first substrate is partially bonded to the second substrate, such that a subset of ic components on the first substrate are bonded to the adhesive areas on the second substrate. the first substrate is then separated from the second substrate, and the subset of ic components bonded to the second substrate are separated from the first substrate and remain on the second substrate.
Inventor(s): Adel Elsherbini of Chandler AZ US for intel corporation, Han Wui Then of Portland OR US for intel corporation, Feras Eid of Chandler AZ US for intel corporation, James E. Jaussi of El Dorado Hills CA US for intel corporation, Ganesh Balamurugan of Hillsboro OR US for intel corporation, Thomas L. Sounart of Chandler AZ US for intel corporation, Johanna Swan of Scottsdale AZ US for intel corporation, Henning Braunisch of Phoenix AZ US for intel corporation, Tushar Kanti Talukdar of Wilsonville OR US for intel corporation, Shawna M. Liff of Scottsdale AZ US for intel corporation
IPC Code(s): H01L21/762, G02B6/30, G02B6/43, H01L21/67, H01L21/683, H01L21/768
CPC Code(s): H01L21/76254
Abstract: methods of selectively transferring integrated circuit (ic) components between substrates, and devices and systems formed using the same, are disclosed herein. in one embodiment, a first substrate with a release layer and a layer of ic components over the release layer is received, and a second substrate with one or more adhesive areas is received. the layer of ic components may include one or more waveguides, ring resonators, drivers, photodetectors, transimpedance amplifiers, and/or electronic integrated circuits. the first substrate is partially bonded to the second substrate, such that a subset of ic components on the first substrate are bonded to the adhesive areas on the second substrate. the first substrate is then separated from the second substrate, and the subset of ic components bonded to the second substrate are separated from the first substrate and remain on the second substrate.
Inventor(s): Bohan Shan of Chandler AZ US for intel corporation, Haobo Chen of Chandler AZ US for intel corporation, Wei Wei of Chandler AZ US for intel corporation, Jose Fernando Waimin Almendares of Gilbert AZ US for intel corporation, Ryan Joseph Carrazzone of Chandler AZ US for intel corporation, Kyle Jordan Arrington of Gilbert AZ US for intel corporation, Ziyin Lin of Chandler AZ US for intel corporation, Dingying Xu of Chandler AZ US for intel corporation, Hongxia Feng of Chandler AZ US for intel corporation, Yiqun Bai of Chandler AZ US for intel corporation, Hiroki Tanaka of Gilbert AZ US for intel corporation, Brandon Christian Marin of Gilbert AZ US for intel corporation, Jeremy Ecton of Gilbert AZ US for intel corporation, Benjamin Taylor Duong of Phoenix AZ US for intel corporation, Gang Duan of Chandler AZ US for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ US for intel corporation, Rui Zhang of Chandler AZ US for intel corporation, Mohit Gupta of Chandler AZ US for intel corporation
IPC Code(s): H01L23/15, H01L23/00, H01L23/13, H01L23/498
CPC Code(s): H01L23/15
Abstract: glass cores including protruding through glass vias and related methods are disclosed herein. an example substrate disclosed herein includes a glass core including a surface and a copper through glass via (tgv) extending through the glass core, the tgv including a protrusion extending from the surface.
Inventor(s): Bozidar Marinkovic of Portland OR US for intel corporation, Benjamin Kriegel of Portland OR US for intel corporation, Payam Amin of Portland OR US for intel corporation, Dolly Natalia Ruiz Amador of Hillsboro OR US for intel corporation, Thomas Jacroux of Hillsboro OR US for intel corporation, Makram Abd El Qader of Hillsboro OR US for intel corporation, Tofizur RAHMAN of Portland OR US for intel corporation, Xiandong Yang of Albuquerque NM US for intel corporation, Conor P. Puls of Portland OR US for intel corporation
IPC Code(s): H01L23/48, H01L23/00, H01L23/528
CPC Code(s): H01L23/481
Abstract: an ic device may include one or more vias for delivering power to one or more transistors in the ic device. a via may have one or more widened ends to increase capacitance and decrease resistance. a transistor may include a source electrode over a source region and a drain electrode over a drain region. the source region or drain region may be in a support structure that has one or more semiconductor materials. the via has a body section and two end sections, the body section is between the end sections. one or both end sections are wider than the body section, e.g., by approximately 6 nanometers to approximately 12 nanometers. one end section is connected to an interconnect at the backside of the support structure. the other end section is connected to a jumper, which is connected to the source electrode or drain electrode.
Inventor(s): Alexander W. HUETTIS of Hillsboro OR US for intel corporation, Patrick NARDI of Scottsdale AZ US for intel corporation, Abid AMEEN of Chandler AZ US for intel corporation, Jiaqi WU of Chandler AZ US for intel corporation, Andrew W. CARLSON of Chandler AZ US for intel corporation
IPC Code(s): H01L23/498
CPC Code(s): H01L23/49816
Abstract: embodiments disclosed herein include systems with interconnects that comprise four or more different interconnect types. in an embodiment, an apparatus comprises a substrate and a ball grid array across a surface of the substrate. in an embodiment, the ball grid array comprises first interconnects in a first region of the ball grid array, second interconnects in a second region of the ball grid array, third interconnects in a third region of the ball grid array, and fourth interconnects in a fourth region of the ball grid array. in an embodiment, the first interconnects, the second interconnects, the third interconnects, and the fourth interconnects all have a difference in one or more of a composition, a dimension, and a structure.
Inventor(s): Yuqin LI of Chandler AZ US for intel corporation, Jesse JONES of Chandler AZ US for intel corporation, Sandrine LTEIF of Phoenix AZ US for intel corporation, Srinivas V. PIETAMBARAM of Chandler AZ US for intel corporation, Suresh Tanaji NARUTE of Chandler AZ US for intel corporation, Pramod MALATKAR of Chandler AZ US for intel corporation, Gang DUAN of Chandler AZ US for intel corporation, Khaled AHMED of San Jose CA US for intel corporation
IPC Code(s): H01L23/498, H01L21/48, H01L23/00, H01L23/15
CPC Code(s): H01L23/49827
Abstract: embodiments disclosed herein include glass cores with vias that are lined by a self-healing liner. in an embodiment, an apparatus comprises a substrate that comprises a solid glass layer with an opening through a thickness of the substrate. in an embodiment, a liner is in contact with a sidewall of the opening, where the liner comprises a polymer matrix with capsules distributed through the polymer matrix. in an embodiment, each capsule comprises a shell, and a core within the shell. in an embodiment, the core comprises an organic material. in an embodiment, a via is in the opening and in contact with the liner, and the via is electrically conductive.
Inventor(s): Pratyush MISHRA of Tempe AZ US for intel corporation, Pratyasha MOHAPATRA of Hillsboro OR US for intel corporation, Srinivas Venkata Ramanuja PIETAMBARAM of Chandler AZ US for intel corporation
IPC Code(s): H01L23/498, H01L23/15, H05K1/02, H05K1/03, H05K1/09, H05K1/11
CPC Code(s): H01L23/49894
Abstract: embodiments disclosed herein include glass cores with through glass vias (tgvs). in an embodiment, an apparatus comprises a substrate that is a solid glass layer, and an opening through a thickness of the substrate. in an embodiment, a via structure is in the opening, where the via structure comprises a first region with an electrically conductive material with a first porosity, and a second region in contact with the first region, where the second region comprises an electrically conductive material with a second porosity that is less than the first porosity. in an embodiment, the second region is separated from a sidewall of the opening by the first region.
Inventor(s): Kimin Jun of Portland OR US for intel corporation, Adel A. Elsherbini of Chandler AZ US for intel corporation, Chia-Ching Lin of Portland OR US for intel corporation, Sou-Chi Chang of Portland OR US for intel corporation, Thomas Lee Sounart of Chandler AZ US for intel corporation, Tushar Kanti Talukdar of Wilsonville OR US for intel corporation, Johanna Marie Swan of Scottsdale AZ US for intel corporation, Uygar Avci of Portland OR US for intel corporation
IPC Code(s): H01L23/522, H01L23/00, H01L23/498, H01L23/528, H01L23/538, H01L25/065, H01L25/16
CPC Code(s): H01L23/5223
Abstract: capacitors for use with integrated circuit packages are disclosed. an example apparatus includes a semiconductor substrate, a metal layer coupled to the semiconductor substrate, a dielectric layer coupled to the metal layer, the dielectric layer including a capacitor disposed therein, and an interface layer positioned between the metal layer and the dielectric layer, the interface layer in contact with the dielectric layer and in contact with the metal layer.
Inventor(s): Abhishek A. Sharma of Portland OR US for intel corporation
IPC Code(s): H01L23/522, H01L23/00
CPC Code(s): H01L23/5226
Abstract: an example ic structure includes a first layer comprising a plurality of transistors; a second layer comprising a stack of layers of one or more insulator materials and conductive interconnect structures extending through the one or more insulator materials; a third layer comprising bonding pads, wherein the second layer is between the first layer and the third layer; and a via continuously extending between one of the bonding pads and one of the conductive interconnect structures in a bottom layer of the stack of layers or a conductive structure in the first layer, wherein the bottom layer is a layer of the stack of layers that is closer to the first layer than all other layers of the stack of layers.
Inventor(s): Su Hwan Kim of Portland OR US for intel corporation, Harish K. Krishnamurthy of Beaverton OR US for intel corporation, Nachiket Desai of Portland OR US for intel corporation, Khondker Ahmed of Hillsboro OR US for intel corporation, Nicolas Butzen of Portland OR US for intel corporation, Krishnan Ravichandran of Saratoga CA US for intel corporation, Kaladhar Radhakrishnan of Chandler AZ US for intel corporation
IPC Code(s): H01L23/522, H01L23/498, H01L25/065, H02M3/335
CPC Code(s): H01L23/5227
Abstract: embodiments herein relate to a voltage regular (vr) formed from die stacked on a package base layer. the die can include a load die stacked on a vr die, with an intermediate layer between the two dies. the vr can include an inductor or transformer as a charge transfer component formed between the dies. for example, the inductor or transformer windings can wind around the intermediate layer and include portions of top metal layers of the vr and load die, where the load die is inverted in the stack. the intermediate layer can be magnetic or non-magnetic for an inductor, or magnetic for a transformer. the vr can optionally be divided among two dies. the vr die may have a gallium nitride substrate to handle a higher input voltage, while the load die comprises a silicon substrate.
Inventor(s): Marvin PAIK of Portland OR US for intel corporation, June CHOI of Portland OR US for intel corporation, Shao Ming KOH of Tigard OR US for intel corporation, Supanee SUKRITTANON of North Plains OR US for intel corporation, Ananya DUTTA of Portland OR US for intel corporation, Sudipto NASKAR of Portland OR US for intel corporation
IPC Code(s): H01L23/528, H01L21/768, H01L23/532
CPC Code(s): H01L23/5283
Abstract: embodiments of the disclosure are in the field of integrated circuit structure fabrication. in an example, an integrated circuit structure includes a plurality of conductive lines on a same level and along a same direction, a first one of the plurality of conductive lines having a first width and a first composition, and a second one of the plurality of conductive lines having a second width and a second composition. the second width greater than the first width, and the second composition is different than the first composition. the second one of the plurality of conductive lines has an uppermost surface above an uppermost surface of the first one of the plurality of conductive lines.
Inventor(s): Jeremy Ecton of Gilbert AZ US for intel corporation, Brandon C. Marin of Gilbert AZ US for intel corporation, Srinivas V. Pietambaram of Chandler AZ US for intel corporation, Bohan Shan of Chandler AZ US for intel corporation, Gang Duan of Chandler AZ US for intel corporation
IPC Code(s): H01L23/538, H01L23/00, H01L23/15, H01L25/065
CPC Code(s): H01L23/5383
Abstract: disclosed herein are microelectronic assemblies and related devices and methods. in some embodiments, a microelectronic assembly may include a glass layer having a surface, the glass layer including conductive through-glass vias (tgvs); a dielectric layer at the surface of the glass layer, the dielectric layer including conductive pathways; and interconnects between the surface of the glass layer and the dielectric layer, wherein individual interconnects electrically couple individual tgvs to individual conductive pathways. in some embodiments, the interconnects include solder or liquid metal ink. in some embodiments, the interconnects include metal-metal bonds and dielectric-dielectric bonds.
Inventor(s): Omkar Karhade of Chandler AZ US for intel corporation, Nitin Ashok Deshpande of Chandler AZ US for intel corporation, Dimitrios Antartis of Hillsboro OR US for intel corporation, Gwang-Soo Kim of Portland OR US for intel corporation, Shawna Marie Liff of Scottsdale AZ US for intel corporation
IPC Code(s): H01L25/065, H01L23/00, H01L23/48
CPC Code(s): H01L25/0652
Abstract: systems, apparatus, and articles of manufacture are disclosed to enable integrated circuit packages with double hybrid bonded dies and methods of manufacturing the same include an integrated circuit (ic) package including a first semiconductor die including first metal vias spaced apart along a first layer of a first dielectric material, the first metal vias connected to respective first metal pads of the first semiconductor die, a second semiconductor die including second metal pads of the second semiconductor die, and a hybrid bond layer including a third dielectric material and third metal vias spaced apart along the third dielectric material, a subset of the third metal vias electrically coupling ones of the first metal pads to respective ones of the second metal pads, a first one of the third metal vias positioned beyond a lateral side of the first semiconductor die.
Inventor(s): Gang Duan of Chandler AZ US for intel corporation, Yosuke Kanaoka of Chandler AZ US for intel corporation, Minglu Liu of Chandler AZ US for intel corporation, Srinivas V. Pietambaram of Chandler AZ US for intel corporation, Brandon C. Marin of Gilbert AZ US for intel corporation, Bohan Shan of Chandler AZ US for intel corporation, Haobo Chen of Chandler AZ US for intel corporation, Jeremy Ecton of Gilbert AZ US for intel corporation, Benjamin T. Duong of Phoenix AZ US for intel corporation, Suddhasattwa Nad of Chandler AZ US for intel corporation
IPC Code(s): H01L25/065, H01L23/00, H01L23/29, H01L23/31, H01L23/42, H01L23/538, H10B80/00
CPC Code(s): H01L25/0655
Abstract: microelectronic assemblies, related devices and methods, are disclosed herein. in some embodiments, a microelectronic assembly may include a first layer having first dies in a first insulating material; a second layer on the first layer, the second layer including second dies having a first thickness and third dies having a second thickness different than the first thickness, the second dies and the third dies in a second insulating material, wherein the second dies and third dies have a first surface and an opposing second surface, and wherein the first surfaces of the second and third dies have a combined surface area between 3,000 square millimeters (mm) and 9,000 mm; and a redistribution layer (rdl) between the first layer and the second layer, the rdl including conductive pathways, wherein the first dies are electrically coupled to the second dies and the third dies by the conductive pathways and by interconnects.
Inventor(s): Gang Duan of Chandler AZ US for intel corporation, Yosuke Kanaoka of Chandler AZ US for intel corporation, Minglu Liu of Chandler AZ US for intel corporation, Srinivas V. Pietambaram of Chandler AZ US for intel corporation, Brandon C. Marin of Gilbert AZ US for intel corporation, Bohan Shan of Chandler AZ US for intel corporation, Haobo Chen of Chandler AZ US for intel corporation, Benjamin T. Duong of Phoenix AZ US for intel corporation, Jeremy Ecton of Gilbert AZ US for intel corporation, Suddhasattwa Nad of Chandler AZ US for intel corporation
IPC Code(s): H01L25/10, H01L23/00, H01L23/29, H01L23/538
CPC Code(s): H01L25/105
Abstract: microelectronic assemblies, related devices and methods, are disclosed herein. in some embodiments, a microelectronic assembly may include a first layer including first dies in a first insulating material; a second layer on the first layer, the second layer including second dies and third dies in a second insulating material, the second dies having a first thickness, the third dies having a second thickness different than the first thickness, and the second dies and the third dies having a surface, wherein the surfaces of the second and third dies have a combined surface area between 3,000 square millimeters (mm) and 9,000 mm; and a redistribution layer (rdl) between the first layer and the second layer, the rdl including conductive pathways through the rdl, wherein the first dies are electrically coupled to the second dies and the third dies by the conductive pathways through the rdl and by interconnects.
Inventor(s): Kasper Wszolek of Gdansk PL for intel corporation, Atul Maheshwari of Portland OR US for intel corporation, Ankireddy Nalamalpu of Portland OR US for intel corporation, Siang Poh Loh of Sungai Petani MY for intel corporation
IPC Code(s): H03K19/177
CPC Code(s): H03K19/177
Abstract: an integrated circuit includes an update controller circuit, updatable logic circuits, and an output circuit. the update controller circuit is configured to control an output signal of the output circuit that is provided to an external conductor during reconfiguration of the updatable logic circuits.
Inventor(s): Sashank Krishnamurthy of Hillsboro OR US for intel corporation
IPC Code(s): H04B1/00, H03K17/687, H04L5/14
CPC Code(s): H04B1/0057
Abstract: embodiments may comprise n-path filter circuitry with tunable radio frequency selectivity and up to 80 decibels per decade roll-off. the n-path filter may comprise at least one input transistor, wherein the at least one input transistor comprises a channel and a gate. a first end of the channel is coupled with a receiver circuitry input, wherein a second end of the channel is coupled with a load. the gate of the at least one input transistor is coupled with a clock circuitry input. the load may comprise a fourth order, all-pole driving point impedance. the impedance may shunt the second end of the channel to a circuit ground or a low voltage circuit rail via the impedance. and the impedance may comprise a first active impedance circuit coupled in series with a second active impedance circuit.
Inventor(s): Ashoke Ravi of Portland OR US for intel corporation, Benjamin Jann of Hillsboro OR US for intel corporation, Satwik Patnaik of Portland OR US for intel corporation, Elan Banin of Raanana M IL for intel corporation, Ofir Degani of Nes-Ammin IL for intel corporation, Alexandros Margomenos of San Jose CA US for intel corporation, Igal Kushnir of Hod-Hasharon IL for intel corporation
IPC Code(s): H04B1/04, G01R27/06, H01Q3/40, H03L7/081, H03L7/24
CPC Code(s): H04B1/0458
Abstract: techniques are described related to digital radio control and operation. the various techniques described herein enable high-frequency local oscillator (lo) signal generation using injection locked cock multipliers (ilcms). the techniques also include the use of lo signals for carrier aggregation applications for phased array front ends. furthermore, the disclosed techniques include the use of array element-level control using per-chain dc-dc converters. still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (adcs) to maximize dynamic range in digital beamforming systems.
Inventor(s): Guotong Wang of Santa Clara CA US for intel corporation, Bishwarup Mondal of San Ramon CA US for intel corporation, Dong Han of Santa Clara CA US for intel corporation, Avik Sengupta of Santa Clara CA US for intel corporation
IPC Code(s): H04B7/0456
CPC Code(s): H04B7/0456
Abstract: systems, apparatuses, methods, and computer-readable media are directed to techniques for codebook support for different antenna structures, such as a user equipment (ue) with a non-uniform antenna array (e.g. with different distances between antenna elements) and/or multiple antenna panels. embodiments further provide techniques for enhanced operation in full power mode 2. for example, embodiments provide techniques for antenna virtualization to form virtual antenna ports from subsets of transmit antennas of the ue (e.g., from eight transmit antennas to two, four, or six virtual antenna ports). other embodiments may be described and claimed.
Inventor(s): Pratik CHANDAK of Dublin CA US for intel corporation, Peng LU of Elk Grove CA US for intel corporation, Thushara HEWAVITHANA of Tempe AZ US for intel corporation, Samuel WONG of Walnut CA US for intel corporation, Michael BEADLE of Tustin CA US for intel corporation
IPC Code(s): H04B17/309, H04L27/26
CPC Code(s): H04B17/346
Abstract: a radio communication device may include: a memory; and a processor configured to: determine a received radio signal including payload information from a plurality of mobile radio communication devices, wherein the payload information is mapped to a resource block via a plurality of cyclic shifts; for each mobile radio communication device of the plurality of mobile radio communication devices, determine a candidate cyclic shift applied to a respective payload information of the payload information, wherein the candidate cyclic shifts for the plurality of mobile radio communication devices are determined from a plurality of candidate cyclic shifts; and perform a noise power estimation using other candidate cyclic shifts of the plurality of candidate cyclic shifts, wherein the other candidate cyclic shifts are not determined as the candidate cyclic shifts.
Inventor(s): Sagar DHAKAL of Los Altos CA US for intel corporation, Yang-Seok CHOI of Portland OR US for intel corporation, Jan SCHRECK of Scotts Valley CA US for intel corporation, Thushara HEWAVITHANA of Tempe AZ US for intel corporation, Nicholas WHINNETT of Bath GB for intel corporation
IPC Code(s): H04L5/00, H04L25/02
CPC Code(s): H04L5/0048
Abstract: a radio communication device may include a memory; and a processor configured to: perform a plurality of channel estimations based on a received radio signal comprising a plurality of reference signals of a plurality of mobile radio communication devices, wherein each channel estimation of the plurality of channel estimations is for a respective mobile radio communication device of the plurality of communication devices; determine a residual signal for the plurality of mobile radio communication devices based on the plurality of channel estimations; and estimate channel information for at least one mobile radio communication device from the plurality of radio communication device based on the residual signal and an estimated power delay profile.
Inventor(s): Yingyang Li of Santa Clara CA US for intel corporation, Yi Wang of Santa Clara CA US for intel corporation, Gang Xiong of Portland OR US for intel corporation, Debdeep Chatterjee of San Jose CA US for intel corporation, Sergey Panteleev of Kildare IE for intel corporation, Salvatore Talarico of Santa Clara CA US for intel corporation
IPC Code(s): H04L5/14, H04W72/1263
CPC Code(s): H04L5/14
Abstract: systems, apparatuses, methods, and computer-readable media are provided for multiple operation modes for downlink (dl) or uplink (ul) transmission in duplex operation, wherein the method comprises: configuring, by a fifth generation (5g) base station (gnb), one or more ul and/or dl resources within a serving cell or bandwidth part (bwp) bandwidth for different symbols; receiving, by a user equipment (ue), an indication of the ul and dl resource configuration; and receiving or transmitting, by a ue, the dl or ul channels/signals, according to the configuration of the dl or ul channels/signals and/or the dci scheduling the dl or ul channels/signals. other embodiments may be described and/or claimed.
Inventor(s): Kapil Sood of Portland OR US for intel corporation, Seosamh O'Riordain of Ennis IE for intel corporation, Ned M. Smith of Beaverton OR US for intel corporation, Tarun Viswanathan of El Dorado Hills CA US for intel corporation
IPC Code(s): H04L9/40, G06F9/4401, G06F9/455, G06F9/46, G06F9/50, G06F21/53, G06F21/57, G06F21/62
CPC Code(s): H04L63/06
Abstract: technologies for providing secure utilization of tenant keys include a compute device. the compute device includes circuitry configured to obtain a tenant key. the circuitry is also configured to receive encrypted data associated with a tenant. the encrypted data defines an encrypted image that is executable by the compute device to perform a workload on behalf of the tenant in a virtualized environment. further, the circuitry is configured to utilize the tenant key to decrypt the encrypted data and execute the workload without exposing the tenant key to a memory that is accessible to another workload associated with another tenant.
Inventor(s): Marcio Juliato of Portland OR US for intel corporation, Manoj Sastry of Portland OR US for intel corporation, Christopher Gutierrez of Hillsboro IN US for intel corporation, Vuk Lesi of Cornelius OR US for intel corporation, Shabbir Ahmed of Portland OR US for intel corporation
IPC Code(s): H04L9/40
CPC Code(s): H04L63/0876
Abstract: techniques to perform time recovery from attacks on delayed authentication in a time synchronized network are described. one embodiment comprises a method for decoding time information and a message authentication code (mac) from a time message, the time information to synchronize a local clock for a device to a network time of a time synchronized network (tsn), and the mac to authenticate the time message, determining whether the time message is authentic using the mac, discarding the time information when the time message is not authentic, performing a bounded search to identify authentic time information using the mac, and passing the authentic time information to a clock manager to synchronize the local clock to the network time of the tsn when the authentic time information is identified. other embodiments are described and claimed.
20250106677. LINK ADAPTATION REPORTING_simplified_abstract_(intel corporation)
Inventor(s): Laurent Cariou of Milizac FR for intel corporation, Thomas J. Kenney of Portland OR US for intel corporation
IPC Code(s): H04W28/02, H04W74/00, H04W84/12
CPC Code(s): H04W28/0236
Abstract: methods, apparatuses, and computer readable media for providing link adaptation information, where a station (sta) comprises processing circuitry configured to: decode, from an access point (ap), a request to send (rts) frame, determine link adaptation information, and encode, for transmission to the ap, a clear-to-send (cts) frame, the cts frame comprising an indication of the link adaptation information. and where an ap comprises processing circuitry configured to: encode, for transmission to a sta, a rts frame, decode, from the sta, a cts frame, the cts frame comprising an indication of the link adaptation information, determining an encoding rate for a ppdu based on the link adaptation information, and encode, for transmission to the sta, the ppdu.
Inventor(s): Gang Xiong of Portland OR US for intel corporation, Guotong Wang of Santa Clara CA US for intel corporation, Prerana Rane of Santa Clara CA US for intel corporation
IPC Code(s): H04W72/232, H04L27/00, H04L27/26, H04W74/0833
CPC Code(s): H04W72/232
Abstract: various embodiments herein provide techniques for dynamic transform precoding indication for a physical uplink shared channel (pusch) transmission and/or a msg3 transmission associated with a random access channel (rach) procedure. for example, a downlink control information (dci) that schedules a pusch may include a field to indicate whether transform precoding is enabled or disabled for the pusch. additionally, or alternatively, the uplink grant received in the msg2 of the rach procedure may include an indication of whether transform precoding is enabled or disabled for the msg3. other embodiments may be described and claimed.
Inventor(s): Kilian Roth of Munich DE for intel corporation, Salvatore Talarico of Santa Clara CA US for intel corporation, Alexey Khoryaev of Santa Clara CA US for intel corporation, Sergey Panteleev of Kildare IE for intel corporation, Mikhail Shilov of Santa Clara CA US for intel corporation
IPC Code(s): H04W72/25, H04L5/00, H04W72/0446
CPC Code(s): H04W72/25
Abstract: various embodiments herein are related to new radio (nr) sidelink (sl) operation in the unlicensed spectrum. specifically, various embodiments may relate to design parameters or implementations of a physical sl control channel (pscch) and/or physical sl shared channel (pssch) in such a network. other embodiments may be described and/or claimed.
Inventor(s): Salvatore Talarico of Santa Clara CA US for intel corporation, Kilian Roth of Munich DE for intel corporation, Alexey Khoryaev of Santa Clara CA US for intel corporation, Sergey Panteleev of Kildare IE for intel corporation, Mikhail Shilov of Santa Clara CA US for intel corporation
IPC Code(s): H04W74/0816, H04L1/1812, H04W92/18
CPC Code(s): H04W74/0816
Abstract: various embodiments herein provide techniques related to adjustment of contention window size for new radio (nr) sidelink (sl) systems. specifically, embodiments may relate to nr sl systems operating in the frequency range 1 (fr-1) unlicensed band, and using type 1 listen-before-talk (lbt). embodiments further relate to lbt bandwidth (bw) definitions in such systems. other embodiments may be described and/or claimed.
20250106982. NANOTWIN LINER FOR THROUGH GLASS VIAS_simplified_abstract_(intel corporation)
Inventor(s): Sashi S. KANDANUR of Phoenix AZ US for intel corporation, Mitchell PAGE of Mesa AZ US for intel corporation, Nicholas S. HAEHN of Scottsdale AZ US for intel corporation, Srinivas Venkata Ramanuja PIETAMBARAM of Chandler AZ US for intel corporation, Steve S. CHO of Chandler AZ US for intel corporation
IPC Code(s): H05K1/02, H01L21/48, H01L23/15, H01L23/498, H05K1/03, H05K1/11
CPC Code(s): H05K1/0271
Abstract: embodiments disclosed herein include glass cores with through glass vias (tgvs). in an embodiment, an apparatus comprises a solid glass layer with an opening through a thickness of the layer, and a via in the opening. in an embodiment, the via comprises a first portion along sidewalls of the opening, where the first portion has a first microstructure, and a second portion in the opening, where the first portion surrounds the second portion, and where the second portion has a second microstructure that is different than the first microstructure.
Inventor(s): Bohan SHAN of Chandler AZ US for intel corporation, Kyle ARRINGTON of Gilbert AZ US for intel corporation, Dingying David XU of Chandler AZ US for intel corporation, Ziyin LIN of Chandler AZ US for intel corporation, Timothy GOSSELIN of Phoenix AZ US for intel corporation, Elah BOZORG-GRAYELI of Tempe AZ US for intel corporation, Aravindha ANTONISWAMY of Chandler AZ US for intel corporation, Wei LI of Chandler AZ US for intel corporation, Haobo CHEN of Chandler AZ US for intel corporation, Yiqun BAI of Chandler AZ US for intel corporation, Jose WAIMIN of Gilbert AZ US for intel corporation, Ryan CARRAZZONE of Chandler AZ US for intel corporation, Hongxia FENG of Chandler AZ US for intel corporation, Srinivas Venkata Ramanuja PIETAMBARAM of Chandler AZ US for intel corporation, Gang DUAN of Chandler AZ US for intel corporation, Bin MU of Tempe AZ US for intel corporation, Mohit GUPTA of Chandler AZ US for intel corporation, Jeremy D. ECTON of Gilbert AZ US for intel corporation, Brandon C. MARIN of Gilbert AZ US for intel corporation, Xiaoying GUO of Chandler AZ US for intel corporation, Ashay DANI of Chandler AZ US for intel corporation
IPC Code(s): H05K1/02, H05K1/03
CPC Code(s): H05K1/0271
Abstract: embodiments disclosed herein include glass core package substrates with a stiffener. in an embodiment, an apparatus comprises a substrate with a first layer with a first width, where the first layer is a glass layer, a second layer under the first layer, where the second layer has a second width that is smaller than the first width, and a third layer over the first layer, where the third layer has a third width that is smaller than the first width. in an embodiment, the apparatus further comprises a metallic structure with a first portion and a second portion, where the first portion is over a top surface of the substrate and the second portion extends away from the first portion and covers at least a sidewall of the first layer.
Inventor(s): Mukund AYALASOMAYAJULA of Chandler AZ US for intel corporation, Jiaqi WU of Chandler AZ US for intel corporation, Andrew W. CARLSON of Chandler AZ US for intel corporation, Matthew MAGNAVITA of Chandler AZ US for intel corporation, Zewei WANG of Chandler AZ US for intel corporation, Xiao LU of Chandler AZ US for intel corporation, George ROBINSON of Chandler AZ US for intel corporation, Brian MOODY of Peoria AZ US for intel corporation, Fatemeh RAHIMI of Chandler AZ US for intel corporation, Chase Williams CHALLE of Gilbert AZ US for intel corporation, Prince Shiva CHAUDHARY of Chandler AZ US for intel corporation, Dhruv Kishor MALDE of Queen Creek AZ US for intel corporation, Mohamed ELHEBEARY of Chandler AZ US for intel corporation
IPC Code(s): H05K1/11, H01L23/00
CPC Code(s): H05K1/11
Abstract: embodiments include an apparatus with interconnects that have different structures. in an embodiment, the apparatus comprises a substrate and a first interconnect on the substrate, a second interconnect on the substrate, and a third interconnect on the substrate. in an embodiment, the first interconnect, the second interconnect, and the third interconnect are all different from each other.
Inventor(s): Ehsan ZAMANI of Phoenix AZ US for intel corporation, Umesh PRASAD of Chandler AZ US for intel corporation, Logan MYERS of Chandler AZ US for intel corporation, Shayan KAVIANI of Phoenix AZ US for intel corporation, Darko GRUJICIC of Chandler AZ US for intel corporation, Elham TAVAKOLI of Phoenix AZ US for intel corporation, Mahdi MOHAMMADIGHALENI of Phoenix AZ US for intel corporation, Rengarajan SHANMUGAM of Tempe AZ US for intel corporation, Rachel Guia GIRON of Mesa AZ US for intel corporation, Srinivas Venkata Ramanuja PIETAMBARAM of Chandler AZ US for intel corporation, Gang DUAN of Chandler AZ US for intel corporation
IPC Code(s): H05K1/11, H01L23/15, H01L23/498, H05K1/03
CPC Code(s): H05K1/116
Abstract: embodiments disclosed herein include glass cores with through glass vias (tgvs). in an embodiment, an apparatus comprises a substrate that is a solid glass layer. in an embodiment, an opening is provided through a thickness of the substrate, and a liner with a first surface is on a sidewall of the opening and a second surface is facing away from the sidewall of the opening. in an embodiment, the liner comprises a matrix, and filler particles in the matrix. in an embodiment, a plurality of cavities are provided into the second surface of the liner. in an embodiment, a via is in the opening, where the via is electrically conductive.
Inventor(s): Chin Mian Choong of Georgetown MY for intel corporation, Jiun Hann Sir of Gelugor MY for intel corporation, Poh Boon Khoo of Perai MY for intel corporation, Wei Jern Tan of Georgetown MY for intel corporation, Boon Ping Koh of Seberang Jaya MY for intel corporation
IPC Code(s): H05K1/18, H01L23/498, H01L25/18, H05K1/14, H05K3/40, H05K3/46, H10B80/00
CPC Code(s): H05K1/181
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed comprising: an integrated circuit package including a package substrate, the package substrate including a first contact and a second contact, the first contact to be electrically coupled to a printed circuit board (pcb); and a timing package distinct from the integrated circuit package, the timing package including a third contact, the third contact to be electrically coupled to the second contact independent of the pcb.
20250107044. PERFORMANCE IN TWO-PHASE COOLING SYSTEMS_simplified_abstract_(intel corporation)
Inventor(s): Jose Diaz Marin of San Jose CR for intel corporation, Fabian Garita Gonzalez of San Rafael CR for intel corporation, Jose Andres Santamaria Cordero of Cartago CR for intel corporation, Ronald Jose Loaiza Baldares of Carago CR for intel corporation, Manfred Humberto Hernandez Calderon of Ciruelas CR for intel corporation, Ruander Cardenas of Portland OR US for intel corporation, Sofia Solis LoĂĄiciga of Guanacaste CR for intel corporation
IPC Code(s): H05K7/20
CPC Code(s): H05K7/20381
Abstract: cooling provided by a thermal management system may be controlled actively to reduce or prevent entering a dry out state. the systems and methods described herein include monitoring temperature metrics and identifying or predicting the onset of a dry out state, and temperature modulation mechanism may be controlled to cause an increase in the temperature of the heat pipe or vapor chamber. by controlling a temperature modulation mechanism to increase the operating temperature, the viscosity of the liquid in the thermal management approach is decreased, which improves its capillary flow and return rate back to the evaporator. by leveraging this temperature-dependent behavior, this thermal control approach may restore cooling capacity by managing the thermal management approach temperature due to a dry out state, and reduce or minimize the computing device performance degradation associated with a dry out state.
Inventor(s): Patrick MORROW of Portland OR US for intel corporation, Seenivasan SUBRAMANIAM of Hillsboro OR US for intel corporation, Anandkumar MAHADEVAN PILLAI of San Jose CA US for intel corporation
IPC Code(s): H10B10/00, H01L23/528
CPC Code(s): H10B10/125
Abstract: structures having stacked transistors with backside access are described. in an example, an integrated circuit structure includes a front side structure. the front side structure includes a device layer including first, second, third and fourth stacks of nanowires and corresponding first, second, third and fourth overlying gate lines, and the device layer including first, second, third, fourth and fifth source or drain structures and corresponding overlying trench contacts alternating with the stacks of nanowires and the overlying gate lines, and one or more metallization layers above the device layer. a backside structure includes a backside via connection coupled to a bottom portion of the third source or drain structure, the bottom portion of the third source or drain structure isolated from a top portion of the third source or drain structure.
20250107107. STACKED MEMORY LAYERS WITH UNIFORM ACCESS_simplified_abstract_(intel corporation)
Inventor(s): Abhishek A. Sharma of Portland OR US for intel corporation, Sagar Suthram of Portland OR US for intel corporation, Wilfred Gomes of Portland OR US for intel corporation, Pushkar Sharad Ranade of San Jose CA US for intel corporation, Anand S. Murthy of Portland OR US for intel corporation, Tahir Ghani of Portland OR US for intel corporation
IPC Code(s): H10B80/00, H01L23/00, H01L25/065, H01L25/18
CPC Code(s): H10B80/00
Abstract: an ic device may include memory layers over a logic layer. a memory layer may include memory arrays and one or more peripheral circuits coupled to the memory arrays. a memory array may include memory cells arranged in rows and columns. a row of memory cells may be associated with a word line. a column of memory cells may be associated with a bit line. the logic layer includes one or more logic circuits that can control data read operations and data write operations of the memory layers. the logic layer may also include a power interconnect, which facilitates power delivery to the memory layers, and a signal interconnect, which facilitates signal transmission within the ic device. the ic device may further include vias that couple the memory layers to the logic layer. each via may be connected to one or more memory layers and the logic layer.
Inventor(s): Abhishek A. Sharma of Portland OR US for intel corporation, Sagar Suthram of Portland OR US for intel corporation, Wilfred Gomes of Portland OR US for intel corporation, Tahir Ghani of Portland OR US for intel corporation, Anand S. Murthy of Portland OR US for intel corporation, Pushkar Sharad Ranade of San Jose CA US for intel corporation
IPC Code(s): H10B80/00, H01L23/00, H01L25/065, H01L25/18
CPC Code(s): H10B80/00
Abstract: an ic device may include memory layers bonded to a logic layer with inclination. an angle between a memory layer and the logic layer may be in a range from approximately 0 to approximately 90 degrees. the memory layers may be over the logic layer. the ic device may include one or more additional logic layers that are parallel to a memory layer or perpendicular to a memory layer. the one or more additional logic layers may be over the logic layer. a memory layer may include memory cells. the logic layer may include logic circuits (e.g., sense amplifier, word line driver, etc.) that control the memory cells. bit lines (or word lines) in different memory layers may be coupled to each other. a bit line and a word line in a memory layer may be controlled by logic circuits in different logic layers.
20250107112. INDUCTORS FOR SEMICONDUCTOR PACKAGE SUBSTRATES_simplified_abstract_(intel corporation)
Inventor(s): Brandon C. MARIN of Gilbert AZ US for intel corporation, Srinivas PIETAMBARAM of Chandler AZ US for intel corporation, Mohammad Mamunur RAHMAN of Gilbert AZ US for intel corporation, Sashi Shekhar KANDANUR of Phoenix AZ US for intel corporation, Aleksandar ALEKSOV of Chandler AZ US for intel corporation, Tarek A. IBRAHIM of Mesa AZ US for intel corporation, Rahul N. MANEPALLI of Chandler AZ US for intel corporation
IPC Code(s): H01L23/48, H01L23/498
CPC Code(s): H10D1/20
Abstract: coaxial magnetic inductor structures useful for semiconductor packaging applications are provided. the coaxial magnetic inductors can be located in semiconductor package cores and the semiconductor package cores can be, for example, comprised of an amorphous solid glass material. methods of manufacturing a coaxial magnetic inductors in a package substrate core are also provided.
Inventor(s): Mahmut Sami Kavrik of Eugene OR US for intel corporation, Uygar E. Avci of Portland OR US for intel corporation, Pratyush P. Buragohain of Hillsboro OR US for intel corporation, Chelsey Dorow of Portland OR US for intel corporation, Jack T. Kavalieros of Portland OR US for intel corporation, Chia-Ching Lin of Portland OR US for intel corporation, Matthew V. Metz of Portland OR US for intel corporation, Wouter Mortelmans of Portland OR US for intel corporation, Carl Hugo Naylor of Portland OR US for intel corporation, Kevin P. O'Brien of Portland OR US for intel corporation, Ashish Verma Penumatcha of Hillsboro OR US for intel corporation, Carly Rogan of North Plains OR US for intel corporation, Rachel A. Steinhardt of Beaverton OR US for intel corporation, Tristan A. Tronic of Aloha OR US for intel corporation, Andrey Vyatskikh of Hillsboro OR US for intel corporation
IPC Code(s): H01L29/786, H01L21/02, H01L21/46, H01L27/092, H01L29/24, H01L29/51, H01L29/66, H01L29/76
CPC Code(s): H10D30/6713
Abstract: hybrid bonding interconnect (hbi) architectures for scalability. embodiments implement a bonding layer on a semiconductor die that includes a thick oxide layer overlaid with a thin layer of a hermetic material including silicon and at least one of carbon and nitrogen. the conductive bonds of the semiconductor die are placed in the thick oxide layer and exposed at the surface of the hermetic material. some embodiments implement a non-bonding moisture seal ring (msr) structure.
Inventor(s): Chiao-Ti Huang of Portland OR US for intel corporation, Robin Chao of Portland OR US for intel corporation, Jaladhi Mehta of Beaverton OR US for intel corporation, Tao Chu of Portland OR US for intel corporation, Guowei Xu of Portland OR US for intel corporation, Ting-Hsiang Hung of Beaverton OR US for intel corporation, Feng Zhang of Hillsboro OR US for intel corporation, Yang Zhang of Rio Rancho NM US for intel corporation, Chia-Ching Lin of Portland OR US for intel corporation, Chung-Hsun Lin of Portland OR US for intel corporation, Anand Murthy of Portland OR US for intel corporation
IPC Code(s): H01L29/786, H01L29/06, H01L29/417, H01L29/423, H01L29/51, H01L29/66
CPC Code(s): H10D30/6757
Abstract: techniques are provided herein to form an integrated circuit having dielectric material formed in cavities beneath source or drain regions. the cavities may be formed within subfin portions of semiconductor devices. in one such example, a fet (field effect transistor) includes a gate structure extending around a fin or any number of nanowires of semiconductor material. the semiconductor material may extend in a first direction between source and drain regions while the gate structure extends over the semiconductor material in a second direction substantially orthogonal to the first direction. a dielectric fill may be formed in a recess beneath the source or drain regions, or a dielectric liner may be formed on sidewalls of the recess, to prevent epitaxial growth of the source or drain regions from the subfins. removal of the semiconductor subfin from the backside may then be performed without causing damage to the source or drain regions.
Inventor(s): Siddharth CHOUKSEY of Portland OR US for intel corporation, Jack T. KAVALIEROS of Portland OR US for intel corporation, Stephen M. CEA of Hillsboro OR US for intel corporation, Ashish AGRAWAL of Beaverton OR US for intel corporation, Willy RACHMADY of Beaverton OR US for intel corporation
IPC Code(s): H01L29/06, H01L27/088, H01L29/417, H01L29/66, H01L29/78
CPC Code(s): H10D62/119
Abstract: neighboring gate-all-around integrated circuit structures having a conductive contact stressor between epitaxial source or drain regions are described. in an example, a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. a first gate stack is over the first vertical arrangement of nanowires. a second gate stack is over the second vertical arrangement of nanowires. first epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. an intervening conductive contact structure is between neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures. the intervening conductive contact structure imparts a stress to the neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures.
Inventor(s): Tao CHU of Portland OR US for intel corporation, Minwoo JANG of Portland OR US for intel corporation, Yanbin LUO of Portland OR US for intel corporation, Paul PACKAN of Hillsboro OR US for intel corporation, Guowei XU of Portland OR US for intel corporation, Chiao-Ti HUANG of Portland OR US for intel corporation, Robin CHAO of Portland OR US for intel corporation, Feng ZHANG of Hillsboro OR US for intel corporation, Ting-Hsiang HUNG of Beaverton OR US for intel corporation, Chia-Ching LIN of Portland OR US for intel corporation, Yang ZHANG of Rio Rancho NM US for intel corporation, Chung-Hsun LIN of Portland OR US for intel corporation, Anand S. MURTHY of Portland OR US for intel corporation
IPC Code(s): H01L29/06, H01L21/8234, H01L21/8238, H01L27/092, H01L29/417, H01L29/423, H01L29/66, H01L29/78
CPC Code(s): H10D62/121
Abstract: integrated circuit structures having reduced local layout effects, and methods of fabricating integrated circuit structures having reduced local layout effects, are described. for example, an integrated circuit structure includes an nmos region including a first plurality of fin structures or vertical stacks of horizontal nanowires, and first alternating gate lines and trench contact structures over the first plurality of fin structures or vertical stacks of horizontal nanowires. the integrated circuit structure also includes a pmos region including a second plurality of fin structures or vertical stacks of horizontal nanowires, and second alternating gate and trench contact structures over the second plurality of fin structures or vertical stacks of horizontal nanowires. a gate line is shared between the nmos region and the pmos region, and a trench contact structure is shared between the nmos region and the pmos region. ends of the gate line shared between the nmos region and the pmos region are offset from ends of the trench contact structure shared between the nmos region and the pmos region.
Inventor(s): Biswajeet GUHA of Hillsboro OR US for intel corporation, Mauro KOBRINSKY of Portland OR US for intel corporation, Patrick MORROW of Portland OR US for intel corporation, Oleg GOLONZKA of Beaverton OR US for intel corporation, Tahir GHANI of Portland OR US for intel corporation
IPC Code(s): H01L29/06, H01L21/02, H01L21/027, H01L21/306, H01L21/84, H01L27/12, H01L29/08, H01L29/10, H01L29/417, H01L29/423, H01L29/66, H01L29/78
CPC Code(s): H10D62/121
Abstract: gate-all-around integrated circuit structures having a removed substrate, and methods of fabricating gate-all-around integrated circuit structures having a removed substrate, are described. for example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. a gate stack surrounds a channel region of the vertical arrangement of horizontal nanowires. a pair of non-discrete epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal nanowires. a pair of dielectric spacers is between the pair of non-discrete epitaxial source or drain structures and the gate stack. the pair of dielectric spacers and the gate stack have co-planar top surfaces. the pair of dielectric spacers, the gate stack and the pair of non-discrete epitaxial source or drain structures have co-planar bottom surfaces.
Inventor(s): Leonard P. GULER of Hillsboro OR US for intel corporation, Gilbert DEWEY of Beaverton OR US for intel corporation, Joseph DâSILVA of Hillsboro OR US for intel corporation, Mauro J. KOBRINSKY of Portland OR US for intel corporation, Ehren MANNEBACH of Tigard OR US for intel corporation, Shaun MILLS of Hillsboro OR US for intel corporation, Charles H. WALLACE of Portland OR US for intel corporation
IPC Code(s): H01L29/08, H01L27/088, H01L29/06, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H10D62/151
Abstract: integrated circuit structures having differentiated source or drain structures are described. in an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. a first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure having a lateral width and a composition. a second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure having the composition of the first epitaxial source or drain structure, and the second epitaxial source or drain structure having a lateral width less than the lateral width of the first epitaxial source or drain structure.
Inventor(s): Leonard P. GULER of Hillsboro OR US for intel corporation, Thomas OâBRIEN of Portland OR US for intel corporation, Anindya DASGUPTA of Portland OR US for intel corporation, Shengsi LIU of Portland OR US for intel corporation, Saurabh ACHARYA of Hillsboro OR US for intel corporation, Charles H. WALLACE of Portland OR US for intel corporation, Baofu ZHU of Portland OR US for intel corporation
IPC Code(s): H01L29/40, H01L29/08, H01L29/417, H01L29/775, H01L29/786
CPC Code(s): H10D64/01
Abstract: integrated circuit structures having trench contact flyover structures, and methods of fabricating integrated circuit structures having trench contact flyover structures, are described. for example, an integrated circuit structure includes a plurality of horizontally stacked nanowires or a fin. a gate structure is over the plurality of horizontally stacked nanowires or the fin. an epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires or the fin. a conductive trench contact structure has a first portion laterally spaced apart from the epitaxial source or drain structure, a second portion vertically over the epitaxial source or drain structure, and a third portion between the first portion and the second portion. a dielectric plug is laterally between the epitaxial source or drain structure and the first portion of the conductive trench contact structure, wherein the third portion of the conductive trench contact structure is vertically over the dielectric plug.
Inventor(s): Yoon Jung Chang of Hillsboro OR US for intel corporation, Zafrullah Jagoo of Aloha OR US for intel corporation, Sridhar Govindaraju of Portland OR US for intel corporation
IPC Code(s): H01L29/49, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/78, H01L29/786
CPC Code(s): H10D64/665
Abstract: techniques are provided to form an integrated circuit having a gate electrode that includes at least one layer containing molybdenum. a transistor includes a gate structure having a gate electrode on a gate dielectric. the gate structure extends around a fin or any number of nanowires (or nanoribbons or nanosheets) of semiconductor material. the gate electrode includes one or more conductive layers on the gate dielectric with at least one of those conductive layers containing molybdenum (e.g., molybdenum nitride). the conductive layer having molybdenum may be used during the formation of the gate dielectric (e.g., during an annealing process), thus resulting in a higher quality gate dielectric.
Inventor(s): Yang Zhang of Rio Rancho NM US for intel corporation, Guowei Xu of Portland OR US for intel corporation, Tao Chu of Portland OR US for intel corporation, Robin Chao of Portland OR US for intel corporation, Chiao-Ti Huang of Portland OR US for intel corporation, Feng Zhang of Hillsboro OR US for intel corporation, Ting-Hsiang Hung of Beaverton OR US for intel corporation, Chia-Ching Lin of Portland OR US for intel corporation, Anand Murthy of Portland OR US for intel corporation
IPC Code(s): H01L29/49, H01L21/28, H01L21/78, H01L29/06, H01L29/417, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H10D64/679
Abstract: techniques are provided to form an integrated circuit having an airgap spacer between at least a transistor gate structure and an adjacent source or drain contact. in one such example, a fet (field effect transistor) includes a gate structure that extends around a fin or any number of nanowires (or nanoribbons or nanosheets, as the case may be) of semiconductor material. the semiconductor material may extend in a first direction between source and drain regions while the gate structure extends over the semiconductor material in a second direction. airgaps are provided in the regions between the gate structures and the adjacent source/drain contacts. the airgaps have a low dielectric constant (e.g., around 1.0) to reduce the parasitic capacitance between the conductive structures.
20250107221. QUANTUM DOT DEVICES_simplified_abstract_(intel corporation)
Inventor(s): James S. Clarke of Portland OR US for intel corporation, Nicole K. Thomas of Leuven BE for intel corporation, Zachary R. Yoscovits of Beaverton OR US for intel corporation, Hubert C. George of Portland OR US for intel corporation, Jeanette M. Roberts of North Plains OR US for intel corporation, Ravi Pillarisetty of Portland OR US for intel corporation
IPC Code(s): H01L27/088, B82Y10/00, H01L21/8234, H01L29/66, H01L29/778, H10N69/00
CPC Code(s): H10D84/83
Abstract: quantum dot devices, and related systems and methods, are disclosed herein. in some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous rows extending in a first direction, and the plurality of second gates are arranged in electrically continuous rows extending in a second direction perpendicular to the first direction.
Inventor(s): Nicole K. THOMAS of Portland OR US for intel corporation, Marko RADOSAVLJEVIC of Portland OR US for intel corporation
IPC Code(s): H01L27/092, H01L21/822, H01L21/8238, H01L29/06, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H10D84/856
Abstract: gate-all-around integrated circuit structures having stacked architectures, and methods of fabricating gate-all-around integrated circuit structures having stacked architectures, are described. for example, an integrated circuit structure includes a first transistor having a first plurality of nanowires of a first composition. a second transistor having a second plurality of nanowires is vertically over and spaced apart from the first plurality of nanowires, the second plurality of nanowires of a second composition different than the first composition. an oxide layer is completely vertically separating the first transistor from the second transistor or an oxide layer only partially vertically separating the first transistor from the second transistor.
Inventor(s): Burak Baylav of Hillsboro OR US for intel corporation, Prabhjot Luthra of Hillsboro OR US for intel corporation, Nidhi Khandelwal of Portland OR US for intel corporation, Marni Nabors of Portland OR US for intel corporation
IPC Code(s): H01L27/02, G06F30/392, G06F30/398, H01L23/528
CPC Code(s): H10D89/10
Abstract: an ic device may include functional regions as well as replica cells and filler cells that can reduce local layout effect in the ic device. a functional region includes functional cells, e.g., logic cell or memory cells. a white space may be between a first functional region and a second functional region. a first portion of the white space may be filled with replica cells, each of which is a replica of a cell in the first functional region. a second portion of the white space may be filled with filler cells that are not functional. the first function region is closer to the replica cells than to the filler cells. a third portion of the white space may be filled with replica cells, each of which is a replica of a cell in the second functional region. the second portion is between the first portion and the third portion.
Inventor(s): Krishna Bharath Kolluru of Hillsboro OR US for intel corporation, Archanna Srinivasan of San Jose CA US for intel corporation
IPC Code(s): H01L27/02, H02H9/04
CPC Code(s): H10D89/811
Abstract: some embodiments include an apparatus having a supply node, a conductive pad, and an electrostatic discharge (esd) protection circuitry. the esd protection circuitry includes a transistor including levels of semiconductor materials separated from each other and located one over another over a substrate. respective portions of the levels of semiconductor materials form part of a channel, a source terminal, and a drain terminal of the transistor. the transistor includes a conductive material separated from the channel by a dielectric material and surrounding at least part of the channel. at least a portion of the conductive material forms part of a gate terminal of the transistor. the gate terminal is coupled to the supply node. the source terminal is coupled to the supply node. and the drain terminal is coupled to the conductive pad.
- Intel Corporation
- G01S7/481
- G01S7/4911
- H01S5/068
- CPC G01S7/4815
- Intel corporation
- G02B6/36
- CPC G02B6/3636
- G02B6/42
- CPC G02B6/423
- CPC G02B6/4231
- G03F1/64
- G03F1/22
- CPC G03F1/64
- G05F1/56
- CPC G05F1/56
- G06F9/30
- CPC G06F9/30014
- G06F9/355
- G06F9/38
- G06F15/78
- CPC G06F9/30036
- CPC G06F9/30167
- G06F9/50
- G06F9/54
- G06F12/084
- G06T1/60
- CPC G06F9/3891
- G06F9/4401
- CPC G06F9/4406
- G06F9/455
- G06F13/38
- G06F13/42
- CPC G06F9/45558
- CPC G06F9/5055
- G06F11/10
- G06F21/64
- CPC G06F11/1064
- G06F12/0802
- G06T1/20
- CPC G06F11/1068
- G06F12/1027
- G06F12/02
- G06F12/121
- CPC G06F12/1027
- G06F12/123
- G06F12/0875
- G06F12/0891
- CPC G06F12/123
- G06F12/14
- G06F12/0808
- CPC G06F12/1408
- G06F21/57
- G06F21/60
- G06F21/76
- G06F21/79
- H04L9/06
- H04L9/08
- H04L9/32
- H04L41/046
- H04L41/28
- G06F13/16
- CPC G06F13/16
- CPC G06F13/4282
- G06F7/544
- G06F7/575
- G06F7/58
- G06F12/06
- G06F12/0804
- G06F12/0811
- G06F12/0862
- G06F12/0866
- G06F12/0871
- G06F12/0882
- G06F12/0888
- G06F12/0893
- G06F12/0895
- G06F12/0897
- G06F12/1009
- G06F12/128
- G06F15/80
- G06F17/16
- G06F17/18
- G06N3/08
- H03M7/46
- CPC G06F15/7839
- G06T15/06
- G06N20/00
- G06F16/334
- CPC G06N20/00
- G06F13/40
- CPC G06T1/20
- G06F12/0806
- G06N3/048
- G06N3/084
- G06T15/00
- G06T11/40
- CPC G06T15/005
- G08G1/16
- B60W50/16
- G01S13/931
- G06V20/58
- CPC G08G1/167
- G09G3/20
- CPC G09G3/2096
- G11C7/10
- CPC G11C7/1063
- G11C11/4091
- G11C11/408
- G11C11/4094
- CPC G11C11/4091
- G11C29/00
- G11C29/52
- CPC G11C29/76
- H01F41/04
- H01L23/498
- H01L23/64
- CPC H01F41/046
- H01H13/807
- G06F1/16
- H01H13/85
- H01H13/86
- H01H13/88
- CPC H01H13/807
- H01L21/50
- H01L21/78
- H01L23/00
- CPC H01L21/50
- H01L21/683
- H01L25/065
- CPC H01L21/6835
- H01L21/762
- G02B6/30
- G02B6/43
- H01L21/67
- H01L21/768
- CPC H01L21/76254
- H01L23/15
- H01L23/13
- CPC H01L23/15
- H01L23/48
- H01L23/528
- CPC H01L23/481
- CPC H01L23/49816
- H01L21/48
- CPC H01L23/49827
- H05K1/02
- H05K1/03
- H05K1/09
- H05K1/11
- CPC H01L23/49894
- H01L23/522
- H01L23/538
- H01L25/16
- CPC H01L23/5223
- CPC H01L23/5226
- H02M3/335
- CPC H01L23/5227
- H01L23/532
- CPC H01L23/5283
- CPC H01L23/5383
- CPC H01L25/0652
- H01L23/29
- H01L23/31
- H01L23/42
- H10B80/00
- CPC H01L25/0655
- H01L25/10
- CPC H01L25/105
- H03K19/177
- CPC H03K19/177
- H04B1/00
- H03K17/687
- H04L5/14
- CPC H04B1/0057
- H04B1/04
- G01R27/06
- H01Q3/40
- H03L7/081
- H03L7/24
- CPC H04B1/0458
- H04B7/0456
- CPC H04B7/0456
- H04B17/309
- H04L27/26
- CPC H04B17/346
- H04L5/00
- H04L25/02
- CPC H04L5/0048
- H04W72/1263
- CPC H04L5/14
- H04L9/40
- G06F9/46
- G06F21/53
- G06F21/62
- CPC H04L63/06
- CPC H04L63/0876
- H04W28/02
- H04W74/00
- H04W84/12
- CPC H04W28/0236
- H04W72/232
- H04L27/00
- H04W74/0833
- CPC H04W72/232
- H04W72/25
- H04W72/0446
- CPC H04W72/25
- H04W74/0816
- H04L1/1812
- H04W92/18
- CPC H04W74/0816
- CPC H05K1/0271
- CPC H05K1/11
- CPC H05K1/116
- H05K1/18
- H01L25/18
- H05K1/14
- H05K3/40
- H05K3/46
- CPC H05K1/181
- H05K7/20
- CPC H05K7/20381
- H10B10/00
- CPC H10B10/125
- CPC H10B80/00
- CPC H10D1/20
- H01L29/786
- H01L21/02
- H01L21/46
- H01L27/092
- H01L29/24
- H01L29/51
- H01L29/66
- H01L29/76
- CPC H10D30/6713
- H01L29/06
- H01L29/417
- H01L29/423
- CPC H10D30/6757
- H01L27/088
- H01L29/78
- CPC H10D62/119
- H01L21/8234
- H01L21/8238
- CPC H10D62/121
- H01L21/027
- H01L21/306
- H01L21/84
- H01L27/12
- H01L29/08
- H01L29/10
- H01L29/775
- CPC H10D62/151
- H01L29/40
- CPC H10D64/01
- H01L29/49
- CPC H10D64/665
- H01L21/28
- CPC H10D64/679
- B82Y10/00
- H01L29/778
- H10N69/00
- CPC H10D84/83
- H01L21/822
- CPC H10D84/856
- H01L27/02
- G06F30/392
- G06F30/398
- CPC H10D89/10
- H02H9/04
- CPC H10D89/811