Texas Instruments Incorporated patent applications on March 20th, 2025
Patent Applications by Texas Instruments Incorporated on March 20th, 2025
Texas Instruments Incorporated: 19 patent applications
Texas Instruments Incorporated has applied for patents in the areas of H01L23/00 (4), G06F11/10 (3), G06F9/30 (3), G06F9/54 (3), G06F13/16 (3) G06F12/128 (2), B60L53/16 (1), H01L24/75 (1), H04N9/3194 (1), H03M1/1245 (1)
With keywords such as: coupled, storage, die, circuit, semiconductor, surface, memory, circuitry, layer, and between in patent application abstracts.
Patent Applications by Texas Instruments Incorporated
Inventor(s): Priyank Anand of Bangalore IN for texas instruments incorporated, Ashish Ojha of Bangalore IN for texas instruments incorporated, Krishnamurthy Shankar of Bangalore IN for texas instruments incorporated, Venkatesh Guduri of Bangalore IN for texas instruments incorporated
IPC Code(s): B60L53/16, B60L53/62
CPC Code(s): B60L53/16
Abstract: examples of contactor controllers, systems and methods enable quick-turn-off (qto) using an output voltage of a contactor controller when its supply voltage is below a threshold but does not interfere with qto when sufficient supply voltage is available. in an example, when vm loss occurs, a high-side (hs) clamp of a contactor controller is disabled, and a low-side (ls) clamp current is generated using the output voltage. the ls clamp current may be adjusted to achieve a desired qto voltage. in another example, a hs clamp is disabled and the charging of the gate of a ls field-effect transistor (fet) is enabled only when the output voltage increases above a power-off qto threshold (less than the ls clamp voltage); the qto voltage is set by a voltage detection and comparison circuit of the contactor controller.
Inventor(s): Adam Joseph Fruehling of Garland TX US for texas instruments incorporated
IPC Code(s): B81B3/00, G02B26/08, H01G5/01, H01H1/00
CPC Code(s): B81B3/0045
Abstract: described embodiments include a microelectromechanical system (mems) array comprising a first mems device that includes a first movable electrostatic plate elastically connected to a first structure, the first movable electrostatic plate having a first mass, a first fixed electrostatic plate, and a first drive circuit having a first drive output coupled to the first fixed electrostatic plate. there is a second mems device that includes a second movable electrostatic plate elastically connected to a second structure, the second movable electrostatic plate having a second mass that is different than the first mass, a second fixed electrostatic plate, and a second drive circuit having a second drive output coupled to the second fixed electrostatic plate.
20250093404. THROUGH-SILICON VIA (TSV) TESTING_simplified_abstract_(texas instruments incorporated)
Inventor(s): Lee D. Whetsel of Parker TX US for texas instruments incorporated
IPC Code(s): G01R31/28, G01R31/3185, H01L21/66, H01L23/48, H01L23/522, H01L23/538
CPC Code(s): G01R31/2853
Abstract: an integrated circuit die includes a substrate of semiconductor material having a top surface, a bottom surface, and an opening through the substrate between the top surface and the bottom surface. a through silicon via (tsv) has a conductive body in the opening, has a top contact point coupled to the body at the top surface, and has a bottom contact point coupled to the body at the bottom surface. a scan cell has a serial input, a serial output, control inputs, a voltage reference input, a response input coupled to one of the contact points, and a stimulus output coupled to the other one of the contact points.
Inventor(s): Kai Chirca of Dallas TX US for texas instruments incorporated, Matthew David Pierson of Frisco TX US for texas instruments incorporated, David E. Smith of Allen TX US for texas instruments incorporated, Timothy David Anderson of University Park TX US for texas instruments incorporated
IPC Code(s): G06F3/06, G06F9/30, G06F9/38, G06F9/48, G06F9/50, G06F12/06, G06F12/0811, G06F12/0815, G06F12/0817, G06F12/0831, G06F12/084, G06F12/0846, G06F12/0855, G06F12/0862, G06F12/0875, G06F12/0891, G06F12/10, G06F12/1009, G06F13/12, G06F13/16, G06F13/40, H03M13/01, H03M13/09, H03M13/15, H03M13/27
CPC Code(s): G06F3/0604
Abstract: techniques including receiving configuration information for a trigger control channel of the one or more trigger control channels, the configuration information defining a first one or more triggering events, receiving a first memory management command, store the first memory management command, detecting a first one or more triggering events, and triggering the stored first memory management command based on the detected first one or more triggering events.
Inventor(s): Kedar Chitnis of Bangalore IN for texas instruments incorporated, Mihir Narendra Mody of Bangalore IN for texas instruments incorporated, Jesse Gregory Villarreal, JR. of Richardson TX US for texas instruments incorporated, Lucas Carl Weaver of Farmers Branch TX US for texas instruments incorporated, Brijesh Jadav of Bangalore IN for texas instruments incorporated, Niraj Nandan of Plano TX US for texas instruments incorporated
IPC Code(s): G06F9/48, G06F9/50, G06F9/54
CPC Code(s): G06F9/4881
Abstract: methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement thread scheduling for multithreaded data processing environments are disclosed. example thread schedulers disclosed herein for a data processing system include a buffer manager to determine availability of respective buffers to be acquired for respective processing threads implementing respective functional nodes of a processing flow, and to identify first ones of the processing threads as stalled due to unavailability of at least one buffer in the respective buffers to be acquired for the first ones of the processing threads. disclosed example thread schedulers also include a thread execution manager to initiate execution of second ones of the processing threads that are not identified as stalled.
Inventor(s): Michael Zwerg of Dallas TX US for texas instruments incorporated, Gregory North of Austin TX US for texas instruments incorporated, Ashwini Gopinath of Bangalore IN for texas instruments incorporated
IPC Code(s): G06F11/10, G06F12/02, G06F13/28
CPC Code(s): G06F11/1004
Abstract: various examples disclosed herein relate to trimming of system elements to prepare the elements for execution of boot code and application code. in an example embodiment, a system is provided. the system includes system control circuitry, direct memory access (dma) circuitry, and processing circuitry. the system control circuitry is configured to instruct the dma circuitry to obtain trim data from memory upon detecting that a first group of system elements has reached an initialized state. the dma circuitry obtains the trim data and writes it to trim registers. the system control circuitry supplies the trim data to a second group of system elements to bring them to an operational level, then instructs the processing circuitry to execute boot code.
Inventor(s): Naveen Bhoria of Plano TX US for texas instruments incorporated, Timothy David Anderson of University Park TX US for texas instruments incorporated, Pete Michael Hippleheuser of Murphy TX US for texas instruments incorporated
IPC Code(s): G06F12/128, G06F9/30, G06F9/54, G06F11/10, G06F12/02, G06F12/0802, G06F12/0804, G06F12/0806, G06F12/0811, G06F12/0815, G06F12/0817, G06F12/0853, G06F12/0855, G06F12/0864, G06F12/0884, G06F12/0888, G06F12/0891, G06F12/0895, G06F12/0897, G06F12/1027, G06F12/12, G06F12/121, G06F12/126, G06F12/127, G06F13/16, G06F15/80, G11C5/06, G11C7/10, G11C7/22, G11C29/42, G11C29/44
CPC Code(s): G06F12/128
Abstract: methods, apparatus, systems and articles of manufacture to reduce bank pressure using aggressive write merging are disclosed. an example apparatus includes a first cache storage; a second cache storage; a store queue coupled to at least one of the first cache storage and the second cache storage and operable to: receive a first memory operation; process the first memory operation for storing the first set of data in at least one of the first cache storage and the second cache storage; receive a second memory operation; and prior to storing the first set of data in the at least one of the first cache storage and the second cache storage, merge the first memory operation and the second memory operation.
Inventor(s): Naveen BHORIA of Plano TX US for texas instruments incorporated, Timothy David Anderson of University Park TX US for texas instruments incorporated, Pete Michael Hippleheuser of Murphy TX US for texas instruments incorporated
IPC Code(s): G06F12/128, G06F9/30, G06F9/54, G06F11/10, G06F12/02, G06F12/0802, G06F12/0804, G06F12/0806, G06F12/0811, G06F12/0815, G06F12/0817, G06F12/0853, G06F12/0855, G06F12/0864, G06F12/0884, G06F12/0888, G06F12/0891, G06F12/0895, G06F12/0897, G06F12/1027, G06F12/12, G06F12/121, G06F12/126, G06F12/127, G06F13/16, G06F15/80, G11C5/06, G11C7/10, G11C7/22, G11C29/42, G11C29/44
CPC Code(s): G06F12/128
Abstract: methods, apparatus, systems and articles of manufacture are disclosed to facilitate fully pipelined read-modify-write support in level 1 data cache using store queue and data forwarding. an example apparatus includes a first storage, a second storage, a store queue coupled to the first storage and the second storage, the store queue operable to receive a first memory operation specifying a first set of data, process the first memory operation for storing the first set of data in at least one of the first storage and the second storage, receive a second memory operation, and prior to storing the first set of data in the at least one of the first storage and the second storage, feedback the first set of data for use in the second memory operation.
20250096034. DAM LAMINATE ISOLATION SUBSTRATE_simplified_abstract_(texas instruments incorporated)
Inventor(s): Chang-Yen Ko of New Taipei City TW for texas instruments incorporated, Chung-Ming Cheng of New Taipei City TW for texas instruments incorporated, Megan Chang of New Taipei City TW for texas instruments incorporated, Chih-Chien HO of New Taipei City TW for texas instruments incorporated
IPC Code(s): H01L21/762, H01L21/306, H01L23/00, H01L23/495, H05K3/38
CPC Code(s): H01L21/76229
Abstract: an apparatus includes a lead frame, a dam and adhesive on portions of the lead frame, and an integrated circuit die having a portion on the dam and another portion on the adhesive. the lead frame can include two portions, or two lead frames. the dam can bridge a space between the two lead frames. the dam can be smaller than the integrated circuit die in at least a width dimension of the dam relative to a width dimension of the integrated circuit die, providing that the integrated circuit die overhangs the dam on each side of the width dimension of the dam. adhesive is located between the integrated circuit die and each lead frame, adjacent to and on each side of the dam. the dam prevents adhesive from spreading into the space between the lead frames.
Inventor(s): Vijaylaxmi Khanolkar of Pune IN for texas instruments incorporated, Yi Yan of San Jose CA US for texas instruments incorporated
IPC Code(s): H01L23/495, H01L23/00, H01L25/00, H01L25/065, H01L25/07
CPC Code(s): H01L23/49568
Abstract: a microelectronic device includes a die pad having a first surface and a second, opposite, surface. a first component is directly attached to the first surface of the die pad through a first thermally conductive material. a second component is directly attached to the second surface of the die pad through a second thermally conductive material. at least a portion of the second component overlaps at least a portion of the first component. the microelectronic device further includes a first thermal shunt connecting the die pad to a first lead, and a second thermal shunt connecting the die pad to a second lead. the first thermal shunt is closer to a center of the first component than to a center of the second component. the second thermal shunt is closer to a center of the second component than to a center of the first component.
Inventor(s): Katleen Fajardo TIMBOL of Allen TX US for texas instruments incorporated, Hung-Yun LIN of Murphy TX US for texas instruments incorporated, Xuan Mo LI of Chengdu CN for texas instruments incorporated
IPC Code(s): H01L23/00, H01L21/027, H01L21/304, H01L21/56, H01L23/31, H01L23/498
CPC Code(s): H01L23/562
Abstract: in examples, a package comprises a semiconductor die having a device side comprising circuitry formed therein. the package comprises a planarized passivation layer abutting the device side and a horizontal metal member coupled to the device side by way of vias extending through the passivation layer. the horizontal metal member has a thickness ranging between 4 microns and 25 microns. the package also comprises a metal post coupled to and vertically aligned with the horizontal metal member without a sputtered seed layer between the metal post and the horizontal metal member. the metal post has a vertical thickness ranging between 10 microns and 80 microns. the package also comprises a polyimide (pi) layer contacting the metal post, the horizontal metal member, and the passivation layer. the pi layer is not positioned between the metal post and the horizontal metal member. a thickness of a thickest portion of the pi layer ranges between 3 microns and 80 microns.
Inventor(s): Chen Chao of CHENGDU CN for texas instruments incorporated, Bo Jiang of CHENGDU CN for texas instruments incorporated, Wei Li of CHENGDU CN for texas instruments incorporated, Jie Chen of CHENGDU CN for texas instruments incorporated, Ruijie Huang of CHENGDU CN for texas instruments incorporated, Liang Zheng of CHENGDU CN for texas instruments incorporated, Qi Ming Bao of CHENGDU CN for texas instruments incorporated, Bin Liu of SHENYANG CN for texas instruments incorporated
IPC Code(s): H01L23/00, B23K3/06
CPC Code(s): H01L24/75
Abstract: an integrated circuit (ic) solder ball mounting apparatus comprises a ball storage unit for storing solder balls, a ball buffer unit configured to receive the solder balls from the ball storage unit in response to one or more pressure-actuated actions, and a gate valve configured to allow the solder balls to transfer to a ball mounting brush configured to place the solder balls onto area array contact structures formed on a wafer containing the integrated circuit.
Inventor(s): Bichoy BAHR of Allen TX US for texas instruments incorporated, Benjamin Stassen COOK of Los Gatos CA US for texas instruments incorporated, Scott R. SUMMERFELT of Garland TX US for texas instruments incorporated
IPC Code(s): H01P3/12, H01L23/31, H01L25/18, H05K1/18
CPC Code(s): H01P3/12
Abstract: in some examples, a package includes a semiconductor die having a first surface and a second surface opposing the first surface, the semiconductor die including circuitry in the first surface. the package also includes an acoustic waveguide in the semiconductor die, the acoustic waveguide including an array of capacitors and a connector coupling the circuitry to the acoustic waveguide.
20250096450. ON-CHIP DIRECTIONAL COUPLER_simplified_abstract_(texas instruments incorporated)
Inventor(s): Tolga Dinc of Dallas TX US for texas instruments incorporated, Swaminathan Sankaran of Allen TX US for texas instruments incorporated, Sachin Kalia of Dallas TX US for texas instruments incorporated
IPC Code(s): H01P5/18
CPC Code(s): H01P5/18
Abstract: an on-chip directional coupler includes a first linear conductive trace, a second linear conductive trace, and a conductive loop. the first linear conductive trace including an end and a coupled port. the second linear conductive trace is spaced apart from and parallel to the first linear conductive trace. the second linear conductive trace includes an end and an isolated port. the conductive loop includes a first end conductively coupled to the end of the first linear conductive trace, and a second end conductively coupled to the end of the second linear conductive trace.
Inventor(s): Yash Shah of Mumbai IN for texas instruments incorporated, Dattatreya Baragur Suryanarayana of Bangalore-Bagmane Lakeview IN for texas instruments incorporated, Bikash Pradhan of Bangalore-Bagmane Lakeview IN for texas instruments incorporated, Mayank Jain of Kodihalli Bangalore IN for texas instruments incorporated
IPC Code(s): H02M3/158, H03K5/24
CPC Code(s): H02M3/158
Abstract: comparator circuitry for power converters. in an example, a circuit includes a comparator having a first comparator input, a second comparator input, and a comparator output, the comparator coupled to a supply terminal. the circuit further includes a first transistor coupled between a boot terminal and the first comparator input and having a control terminal coupled to a switching terminal, and a second transistor coupled between the boot terminal and the second comparator input and having a control terminal coupled to the switching terminal. also, a third transistor is coupled between the supply terminal and the second comparator input, and a voltage reference generator is coupled to the supply terminal and to a control terminal of the third transistor.
Inventor(s): Anindya PODDAR of Sunnyvale CA US for texas instruments incorporated, Hau NGUYEN of San Jose CA US for texas instruments incorporated, Masamitsu MATSUURA of Beppu JP for texas instruments incorporated
IPC Code(s): H03H9/02, H03H3/007, H03H3/04, H03H9/05, H03H9/10, H03H9/17, H03H9/24
CPC Code(s): H03H9/02133
Abstract: in examples, a device comprises a semiconductor die, a thin-film layer, and an air cavity positioned between the semiconductor die and the thin-film layer. the air cavity comprises a resonator positioned on the semiconductor die. a rib couples to a surface of the thin-film layer opposite the air cavity.
Inventor(s): Sai Aditya Nurani of Bengaluru IN for texas instruments incorporated, Rishi Soundararajan of Bangalore IN for texas instruments incorporated, Nithin Gopinath of Bangalore IN for texas instruments incorporated, Visvesvaraya Pentakota of Bangalore IN for texas instruments incorporated, Shagun Dusad of Bangalore IN for texas instruments incorporated
IPC Code(s): H03M1/12, H03M1/44, H03M1/50, H03M1/78
CPC Code(s): H03M1/1245
Abstract: an analog-to-digital converter circuit incorporating includes a multi-bit input buffer having a differential input and configured to generate, at a plurality of differential outputs, a plurality of residues of a differential input sample relative to a corresponding plurality of zero-crossing references. chopping stages chop the residues, for example with a pseudo-random binary sequence. the circuit further includes zero-crossing comparators, each with differential inputs coupled to receive one of the chopped residues. the zero-crossing comparators are in an ordered sequence of zone thresholds within the input range of the circuit. folding logic circuitry has inputs coupled to outputs of the comparators, and outputs a delay domain signal indicating a magnitude of the one of the residues relative to a nearest zone threshold. digital stage circuitry generates a digital output word representing the received input sample responsive to the comparator outputs and the delay domain signal.
Inventor(s): Jaime De La Cruz of Carrollton TX US for texas instruments incorporated, Jeffrey Kempf of Dallas TX US for texas instruments incorporated, Shivam Srivastava of Bangalore IN for texas instruments incorporated
IPC Code(s): H04N9/31, G06T7/90, H04N23/61
CPC Code(s): H04N9/3194
Abstract: a system including at least one processor configured to determine a command pattern and a projector coupled to the at least one processor. the projector is configured to project an opening pattern, project the command pattern after projecting the opening pattern, and project a closing pattern after projecting the command pattern.
Inventor(s): Zhikai Tang of Sunnyvale CA US for texas instruments incorporated, Jungwoo Joh of Allen TX US for texas instruments incorporated, Ujwal Radhakrishna of San Jose CA US for texas instruments incorporated
IPC Code(s): H01L29/417, H01L29/20, H01L29/40, H01L29/66, H01L29/778
CPC Code(s): H10D64/254
Abstract: semiconductor devices with a source contact extending into a substrate are described. in one example, a semiconductor device comprises a semiconductor substrate including a source region, a gate region, a drain region, and a drain access region, where a heterojunction structure is disposed over the semiconductor substrate. the heterojunction structure includes a buffer layer over the semiconductor substrate and a barrier layer over the buffer layer. a gate stack is disposed over the barrier layer in the gate region. a source contact in the source region extends into the semiconductor substrate, including a first contact with a 2deg in the heterojunction structure and a second contact with the semiconductor substrate.
Texas Instruments Incorporated patent applications on March 20th, 2025
- Texas Instruments Incorporated
- B60L53/16
- B60L53/62
- CPC B60L53/16
- Texas instruments incorporated
- B81B3/00
- G02B26/08
- H01G5/01
- H01H1/00
- CPC B81B3/0045
- G01R31/28
- G01R31/3185
- H01L21/66
- H01L23/48
- H01L23/522
- H01L23/538
- CPC G01R31/2853
- G06F3/06
- G06F9/30
- G06F9/38
- G06F9/48
- G06F9/50
- G06F12/06
- G06F12/0811
- G06F12/0815
- G06F12/0817
- G06F12/0831
- G06F12/084
- G06F12/0846
- G06F12/0855
- G06F12/0862
- G06F12/0875
- G06F12/0891
- G06F12/10
- G06F12/1009
- G06F13/12
- G06F13/16
- G06F13/40
- H03M13/01
- H03M13/09
- H03M13/15
- H03M13/27
- CPC G06F3/0604
- G06F9/54
- CPC G06F9/4881
- G06F11/10
- G06F12/02
- G06F13/28
- CPC G06F11/1004
- G06F12/128
- G06F12/0802
- G06F12/0804
- G06F12/0806
- G06F12/0853
- G06F12/0864
- G06F12/0884
- G06F12/0888
- G06F12/0895
- G06F12/0897
- G06F12/1027
- G06F12/12
- G06F12/121
- G06F12/126
- G06F12/127
- G06F15/80
- G11C5/06
- G11C7/10
- G11C7/22
- G11C29/42
- G11C29/44
- CPC G06F12/128
- H01L21/762
- H01L21/306
- H01L23/00
- H01L23/495
- H05K3/38
- CPC H01L21/76229
- H01L25/00
- H01L25/065
- H01L25/07
- CPC H01L23/49568
- H01L21/027
- H01L21/304
- H01L21/56
- H01L23/31
- H01L23/498
- CPC H01L23/562
- B23K3/06
- CPC H01L24/75
- H01P3/12
- H01L25/18
- H05K1/18
- CPC H01P3/12
- H01P5/18
- CPC H01P5/18
- H02M3/158
- H03K5/24
- CPC H02M3/158
- H03H9/02
- H03H3/007
- H03H3/04
- H03H9/05
- H03H9/10
- H03H9/17
- H03H9/24
- CPC H03H9/02133
- H03M1/12
- H03M1/44
- H03M1/50
- H03M1/78
- CPC H03M1/1245
- H04N9/31
- G06T7/90
- H04N23/61
- CPC H04N9/3194
- H01L29/417
- H01L29/20
- H01L29/40
- H01L29/66
- H01L29/778
- CPC H10D64/254