18478855. DISAGGREGATED PROCESSOR ARCHITECTURES USING SELECTIVE TRANSFER TECHNOLOGY (INTEL CORPORATION)
DISAGGREGATED PROCESSOR ARCHITECTURES USING SELECTIVE TRANSFER TECHNOLOGY
Organization Name
Inventor(s)
Adel Elsherbini of Chandler AZ US
Julien Sebot of Portland OR US
Johanna Swan of Scottsdale AZ US
Shawna M. Liff of Scottsdale AZ US
Carleton L. Molnar of Northborough MA US
Tushar Kanti Talukdar of Wilsonville OR US
DISAGGREGATED PROCESSOR ARCHITECTURES USING SELECTIVE TRANSFER TECHNOLOGY
This abstract first appeared for US patent application 18478855 titled 'DISAGGREGATED PROCESSOR ARCHITECTURES USING SELECTIVE TRANSFER TECHNOLOGY
Original Abstract Submitted
An embodiment discloses a processor comprising a first die comprising at least one of a processing core or a field programmable gate array, a second die comprising at least a portion of an L1 cache, an L2 cache, or both an L1 cache and an L2 cache, and wherein the first die or the second die is bonded to an adhesive area.
Categories:
- INTEL CORPORATION
- Adel Elsherbini of Chandler AZ US
- Julien Sebot of Portland OR US
- Johanna Swan of Scottsdale AZ US
- Shawna M. Liff of Scottsdale AZ US
- Carleton L. Molnar of Northborough MA US
- Tushar Kanti Talukdar of Wilsonville OR US
- H01L25/065
- G06F12/0811
- G06F12/0897
- H01L23/00
- H01L23/498
- H01L23/538
- H10B80/00
- CPC H01L25/0652