Advanced Micro Devices, Inc. patent applications on April 3rd, 2025
Patent Applications by Advanced Micro Devices, Inc. on April 3rd, 2025
Advanced Micro Devices, Inc.: 47 patent applications
Advanced Micro Devices, Inc. has applied for patents in the areas of G06T15/04 (4), G06F3/06 (4), G06F13/16 (4), G06T15/80 (4), G06T15/00 (3) G06T15/80 (4), G06T15/06 (3), G06F12/0811 (2), G06F12/0897 (2), G06T1/20 (2)
With keywords such as: memory, data, cache, space, based, processor, processing, shade, performing, and request in patent application abstracts.
Patent Applications by Advanced Micro Devices, Inc.
Inventor(s): Paul Blinzer of Bellevue WA US for advanced micro devices, inc., Maulik Ojas Mankad of Bangalore IN for advanced micro devices, inc., Victor Ignatski of Markham CA for advanced micro devices, inc., Ashish Jain of Austin TX US for advanced micro devices, inc., Gia Phan of Markham CA for advanced micro devices, inc., Ranjeet Kumar of Markham CA for advanced micro devices, inc.
IPC Code(s): G06F1/08, G06F21/64, G06F21/73, H01L23/525
CPC Code(s): G06F1/08
Abstract: a computer-implemented method for enabling a feature of a semiconductor device can include receiving, by at least one processor of a semiconductor device, a command to enable a feature of the semiconductor device. the method can also include burning, by the at least one processor and in response to the command, an electronic fuse of the semiconductor device. various other methods, systems, and computer-readable media are also disclosed.
20250110538. GRANULAR POWER GATING OVERRIDE_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): Meeta Surendramohan Srivastav of Austin TX US for advanced micro devices, inc., Indrani Paul of Austin TX US for advanced micro devices, inc., Akila Subramaniam of Austin TX US for advanced micro devices, inc.
IPC Code(s): G06F1/3203
CPC Code(s): G06F1/3203
Abstract: the disclosed device includes a processing component having various compute blocks, and a control circuit that switches at least one of the compute blocks from a normal voltage rail for the processing component to a second voltage rail in response to power gating a normal voltage rail. various other methods, systems, and computer-readable media are also disclosed.
Inventor(s): Johnathan Robert Alsop of Seattle WA US for advanced micro devices, inc., Shaizeen Dilawarhusen Aga of Santa Clara CA US for advanced micro devices, inc., Khaled Hamidouche of Austin TX US for advanced micro devices, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0622
Abstract: non-blocking processing system are described. in accordance with the described techniques, a pending range store receives, at a start of a bulk memory operation, a pending memory range of the bulk memory operation. a logic unit includes at least one of check conflict logic or check address logic. the logic unit detects a conflicting memory access based on a target address of the pending memory range conflicting with a memory access request separate from the bulk memory operation. the logic unit performs at least a portion of the bulk memory operation associated with the target address before the memory access request is allowed to proceed.
Inventor(s): Jagadish B. Kotra of Austin TX US for advanced micro devices, inc., Divya Madapusi Srinivas Prasad of San Mateo CA US for advanced micro devices, inc.
IPC Code(s): G06F3/06, G11C11/22, H10B53/30
CPC Code(s): G06F3/0652
Abstract: efficient memory operation using a destructive read memory array is described. in accordance with the described techniques, a system may include a memory configured to store data of a first logic state in a ferroelectric capacitor when an electric polarization of the ferroelectric capacitor is in a first direction. a system may include a controller configured to erase the data from the memory by commanding the electric polarization of the ferroelectric capacitor in a second direction, opposite of the first direction and skipping a subsequent write operation of a null value to the memory.
20250110663. REFRESH DURING POWER STATE CHANGES_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): Jean J. Chittilappilly of Maynard MA US for advanced micro devices, inc., Kevin M. Brandl of Austin TX US for advanced micro devices, inc., Jing Wang of Austin TX US for advanced micro devices, inc., Kedarnath Balakrishnan of Bangalore IN for advanced micro devices, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0658
Abstract: a data processor that is operable to be coupled to a memory includes a memory operation array, a controller, a refresh logic circuit, and a selector. the memory operation array is for storing memory operations for a first power state of the memory. the controller is responsive to a power state change request to execute a plurality of memory operations from the memory operation array when the first power state is selected. the refresh logic circuit generates refresh cycles periodically for the memory. the selector is for multiplexing the refresh cycles with the memory operations during a power state change to the first power state.
Inventor(s): Guanhao Shen of Austin TX US for advanced micro devices, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: a memory controller includes a command queue for receiving memory access requests and an arbiter. the arbiter is operable to allow cross-mode activations during a streak of accesses of a current mode in response to a number of cross-mode accesses present in the command queue exceeding an adaptive threshold.
Inventor(s): Pravesh Gupta of Bangalore IN for advanced micro devices, inc., Benjamin Tsien of Santa Clara CA US for advanced micro devices, inc.
IPC Code(s): G06F9/48, G06F1/3296
CPC Code(s): G06F9/4831
Abstract: the disclosed device includes a heterogeneous processor architecture having heterogeneous processors, and a control circuit that can assign, in response to an interrupt, the interrupt to one of the heterogenous processors that is selected based on power efficiency. various other methods, systems, and computer-readable media are also disclosed.
20250110776. HARDWARE QUEUE PRIORITY MECHANISM_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): Fabian Robert Sebastian Wildgrube of Mönkeberg DE for advanced micro devices, inc., Matthaeus G. Chajdas of Munich DE for advanced micro devices, inc.
IPC Code(s): G06F9/48, G06F9/54
CPC Code(s): G06F9/4881
Abstract: a processing system includes dispatch circuitry that sends elements to one or more processing circuits such as shader circuitry for execution. the dispatch circuitry includes a dispatch queue and an arbitration circuit. the dispatch queue stores the elements to be sent to the one or more processing circuits. the arbitration circuit schedules the elements of the dispatch queue for execution based on priority indicators corresponding to the elements. as a result, prioritization of the elements is implemented at the dispatch circuitry in hardware without changing a design of the dispatch queue to store the priority information.
Inventor(s): Stephen Alexander Zekany of Redmond WA US for advanced micro devices, inc., Anthony Thomas Gutierrez of Seattle WA US for advanced micro devices, inc.
IPC Code(s): G06F9/50
CPC Code(s): G06F9/5033
Abstract: in accordance with the described techniques, a host processor receives a task graph including tasks and indicating dependencies between the task graph. the host processor formats the task graph, in part, by sorting the tasks of the task graph in an order based on the dependencies between the tasks. further, the host processor submits the formatted task graph to a scalable input/output virtualization (siov) device, which directs the siov device to process the tasks of the task graph based on the order.
Inventor(s): David Joseph Clinton of Coopersburg PA US for advanced micro devices, inc.
IPC Code(s): G06F11/07, G06F11/10
CPC Code(s): G06F11/0772
Abstract: memory access validation for input/output operations using an interposer is described. in one or more implementations, an interposer is disposed logically between an input/output device and a memory. the interposer receives a plurality of requests from the input/output device to access the memory non-sequentially in association with an input/output operation. responsive to each request, the interposer updates an accumulated error code using error-detection logic. based upon the accumulated error code, the interposer outputs an i/o validity indicator.
Inventor(s): Moumita Dey of San Jose CA US for advanced micro devices, inc., Varun Agrawal of Westford MA US for advanced micro devices, inc.
IPC Code(s): G06F12/02
CPC Code(s): G06F12/023
Abstract: in accordance with the described techniques for data compression using reconfigurable hardware based on data redundancy patterns, a computing device includes a memory, processing-in-memory units, a host processing unit, and a compression unit having reconfigurable logic for performing multiple compression algorithms. the host processing unit issues processing-in-memory requests instructing the processing-in-memory units to scan a block of the memory for one or more data redundancy patterns, and to identify a compression algorithm of the multiple compression algorithms based on the one or more data redundancy patterns. further, the host processing unit issues a memory request to access a memory address in the block of the memory. the memory request causes data of the memory address to be communicated from the block of the memory to the compression unit to be compressed using the compression algorithm.
Inventor(s): Anwar Parvez Kashem of Sudbury MA US for advanced micro devices, inc., Alicia Wen Ju Yurie Leong of Austin TX US for advanced micro devices, inc., Glennis Eliagh Covington of Austin TX US for advanced micro devices, inc.
IPC Code(s): G06F12/02, G06F13/16, G11C11/4076
CPC Code(s): G06F12/023
Abstract: enhanced methods for memory context restore are described. a device may include a physical layer (phy) having an interface to support communication of command signals and data with a physical memory. the phy implements a training mode to train the interface, detect values of a plurality of parameters as part of training the interface, and store the detected values as initial training data. the phy also implements a retraining mode to use the initial training data as seed data to retrain the interface.
Inventor(s): Srikanth Reddy Gruddanti of Bangalore IN for advanced micro devices, inc., Krishnaiah Gummidipudi of Bangalore IN for advanced micro devices, inc., Prasant Kumar Vallur of Hyderabad IN for advanced micro devices, inc., David Hugh McIntyre of Santa Clara CA US for advanced micro devices, inc., Ramon Apostol Mangaser of Boxborough MA US for advanced micro devices, inc.
IPC Code(s): G06F12/0811
CPC Code(s): G06F12/0811
Abstract: an accelerated processor includes a processor core die including a plurality of compute units, the plurality of compute units including a first level (l1) cache. the accelerated processor also includes a plurality of memory cache dies coupled to the processor core die, the plurality of memory cache dies including a last level cache (llc) such as a level 3 (l3) cache. the accelerated processor includes an llc controller to issue a cache access request to the llc and, based on a latency of the cache access request, direct the cache access request to a subset of the plurality of memory cache dies.
Inventor(s): William L. Walker of Ft Collins CO US for advanced micro devices, inc., Scott Thomas Bingham of Santa Clara CA US for advanced micro devices, inc., Pongstorn Maidee of San Jose CA US for advanced micro devices, inc., William E. Jones of Ft Collins CO US for advanced micro devices, inc., Richard Carlson of Santa Clara CA US for advanced micro devices, inc.
IPC Code(s): G06F12/0811, G06F12/1027
CPC Code(s): G06F12/0811
Abstract: the disclosed device includes a processor and an interconnect connecting the processor to a memory. the interconnect includes an interconnect agent that can forward memory requests from the processor to the memory and receive requested data returned by the memory. the requested data can include information for a next memory request such that the interconnect agent can send, to the memory, a speculative memory request using information for the next memory request that was received in response to the memory request. various other methods, systems, and computer-readable media are also disclosed.
Inventor(s): Travis Henry Boraten of Austin TX US for advanced micro devices, inc., Jagadish B. Kotra of Austin TX US for advanced micro devices, inc., David Andrew Werner of Austin TX US for advanced micro devices, inc.
IPC Code(s): G06F12/0815
CPC Code(s): G06F12/0815
Abstract: selectively bypassing cache directory lookups for processing-in-memory instructions is described. in one example, a system maintains information describing a status—clean or dirty—of a memory address, where a dirty status indicates that the memory address is modified in a cache and thus different than the memory address as represented in system memory. a processing-in-memory request involving the memory address is assigned a cache directory bypass bit based on the status of the memory address. the cache directory bypass bit for a processing-in-memory request controls whether a cache directory lookup is performed after the processing-in-memory request is issued by a processor core and before the processing-in-memory request is executed by a processing-in-memory component.
Inventor(s): Shaizeen Dilawarhusen Aga of Santa Clara CA US for advanced micro devices, inc., Nuwan S. Jayasena of Cupertino CA US for advanced micro devices, inc., Michael J. Schulte of Austin TX US for advanced micro devices, inc., Srilatha Manne of Seattle WA US for advanced micro devices, inc.
IPC Code(s): G06F12/0891, G06F12/0877
CPC Code(s): G06F12/0891
Abstract: systems and techniques for selectively transferring one or more portions of a cache block in response to a request are described. computing system components are informed as to instances where data transfer operations involve moving less than an entirety of data included in a cache block cache block. in one example, executable code for a computational task includes hints that identify when memory requests involve accessing and transmitting less than an entirety of a cache block and cause system components to communicate a subset of the cache block during a memory access. in another example, a data differentiator unit is implemented to analyze a cache block and return a portion of the cache block that is selected based on one or more criteria specified for a computational task. the described techniques thus overcome conventional drawbacks facing systems that transmit an entire cache block when only a portion is needed.
Inventor(s): Travis Henry Boraten of Austin TX US for advanced micro devices, inc., Jagadish B. Kotra of Austin TX US for advanced micro devices, inc., David Andrew Werner of Austin TX US for advanced micro devices, inc.
IPC Code(s): G06F12/0897, G06F12/0891
CPC Code(s): G06F12/0897
Abstract: speculative cache invalidation techniques for processing-in-memory instructions are described. in one example, a system includes a cache system including a plurality of cache levels and a cache coherence controller. the cache coherence controller is configured to perform a cache directory lookup using a cache directory. the cache directory lookup is configured to indicate whether data associated with a memory address specified by a processing-in-memory request is valid in memory. the system employs speculative evaluation logic to identify whether the data associated with the processing-in-memory request is stored in the cache system before the processing-in-memory request is transmitted to the cache coherence controller. if the data is stored in the cache system, the cache system locally invalidates or flushes the data to avoid stalling the processing-in-memory request during a cache directory lookup.
Inventor(s): David Andrew Werner of Austin TX US for advanced micro devices, inc., Travis Henry Boraten of Austin TX US for advanced micro devices, inc., Michael Warren Boyer of Redmond WA US for advanced micro devices, inc.
IPC Code(s): G06F12/0897, G06F12/0891
CPC Code(s): G06F12/0897
Abstract: preemptive flushing of data involved in executing a processing-in-memory command, from a cache system to main memory that is accessible by a processing-in-memory component, is described. in one example, a system includes an asynchronous flush controller that receives an indication of a subsequent processing-in-memory command to be executed as part of performing a computational task. while earlier commands of the computational task are executed, the asynchronous flush controller evicts or invalidates data elements involved in executing the subsequent processing-in-memory command from the cache system, such that the processing-in-memory command can proceed without stalling.
Inventor(s): Tomasz Bogdan Madajczak of Gdansk PL for advanced micro devices, inc.
IPC Code(s): G06F12/10
CPC Code(s): G06F12/10
Abstract: an apparatus and method for efficiently managing memory requests. an integrated circuit includes multiple compute circuits, each capable of processing a data block of multiple data blocks. an amount of available data storage space of a cache is smaller than storage space in a memory for storing the multiple data blocks. in various implementations, the multiple compute circuits process data blocks in a contiguous manner, and pointer updating circuitry assigns data block identifiers in a contiguous manner. the circuitry updates the pointer of an initial data block to use for a particular stage of data processing to a value which increases cache hits during the particular stage of data processing. the circuitry accounts for the number of data blocks of intermediate results to increase or decrease for a particular stage of data processing when updating the pointers.
20250110893. CACHE VIRTUALIZATION_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): John Szeto of Santa Clara CA US for advanced micro devices, inc., Anthony Asaro of Markham CA for advanced micro devices, inc., Kostantinos Danny Christidis of Toronto CA for advanced micro devices, inc., Wade K. Smith of Sunnyvale CA US for advanced micro devices, inc.
IPC Code(s): G06F12/1027, G06F12/0873
CPC Code(s): G06F12/1027
Abstract: an apparatus and method for efficiently performing address translation requests. an integrated circuit includes a system memory that stores address mappings, and the circuitry of one or more clients processes one or more applications and generate address translation requests. a translation lookaside buffer (tlb) stores, in multiple entries, address mappings retrieved from the system memory. circuitry of a client processes one or more applications and generates address translation requests. the entries of the tlb stores address mappings corresponding to different address mapping types and different virtual functions to avoid searches of multiple other lower-level tlbs that are significantly larger and have larger access. in addition, the tlb is implemented with a relatively small number of entries and uses fully associative data storage arrangement to further reduce access latencies.
Inventor(s): Mark Evan Wilkening of Cambridge MA US for advanced micro devices, inc.
IPC Code(s): G06F12/1045
CPC Code(s): G06F12/1045
Abstract: scratchpad memory translation lookaside buffer techniques are described. in an implementation, the techniques described herein relate to a device including a memory management unit implemented in hardware of an integrated circuit to receive a mapping instruction from a mapping instruction source, the mapping instruction specifying a mapping between a virtual memory address and a physical memory address of a scratchpad memory and store a virtual-to-physical mapping entry in a translation lookaside buffer based on the mapping instruction.
20250110895. CONFIGURABLE CACHE REPLACEMENT_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): Ian Richard Beaumont of Sydney AU for advanced micro devices, inc.
IPC Code(s): G06F12/122
CPC Code(s): G06F12/122
Abstract: the disclosed device includes a cache organized by sets and ways and a control circuit that selects a first way for a cache replacement from a first half of a set of ways. the control circuit also selects another way from a second half of the set of ways, and uses the second way for the cache replacement when the first way is unavailable. various other methods, systems, and computer-readable media are also disclosed.
Inventor(s): Shaizeen Dilawarhusen Aga of Santa Clara CA US for advanced micro devices, inc., Mahzabeen Islam of Dripping Springs TX US for advanced micro devices, inc., Nuwan S. Jayasena of Cupertino CA US for advanced micro devices, inc.
IPC Code(s): G06F13/16, G06F13/42
CPC Code(s): G06F13/1668
Abstract: method and apparatus for collaborative memory accesses is described. a system includes a memory controller that receives a command from a host. the command is associated with at least one of a plurality of data elements. the memory controller causes execution of data casting operations that adjust a bit size of the plurality of data elements to generate casted data elements. the system includes an interface for communicating data between the host and a memory.
20250110899. IN-SWITCH EMBEDDING BAG POOLING_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): Kishore Punniyamurthy of Austin TX US for advanced micro devices, inc., Khaled Hamidouche of Austin TX US for advanced micro devices, inc., Brandon K. Potter of Troup TX US for advanced micro devices, inc.
IPC Code(s): G06F13/16, G06F12/02, G06N3/08
CPC Code(s): G06F13/1668
Abstract: an apparatus and method for reducing the memory bandwidth of executing machine learning models. a computing system includes two or more processing nodes, each including at least one or more processors and a corresponding local memory. switch circuitry communicates with at least the local memories and a system memory of the computing system. the switch includes multiple direct memory access (dma) interfaces. each of one or more processing nodes stores multiple embedding rows of embedding tables. a processor of the processing node identifies two or more embedding rows as source operands of a reduction operation. the switch executes memory access requests to retrieve data of the two or more embedding rows from the corresponding local memory, and generates a result by performing the reduction operation. the switch sends the result to the local memory.
Inventor(s): QING LI of SHANGHAI CN for advanced micro devices, inc., BUHENG XU of BEIJING CN for advanced micro devices, inc.
IPC Code(s): G06F13/40, G06F12/06, G06F13/42
CPC Code(s): G06F13/404
Abstract: an apparatus includes a controller that generates a configuration base address register (bar) allocation lookup table in a first memory, such as sram. the configuration bar allocation lookup table includes at least one bar configuration entry associated with each of a plurality of peripheral devices wherein each bar configuration entry includes configuration data for configuring at least one corresponding physical bar associated with a corresponding peripheral device. the controller configures one or more physical bars based on the configuration data in the configuration bar allocation lookup table. associated methods are also presented.
Inventor(s): Mohamed Assem Abd ElMohsen Ibrahim of Santa Clara CA US for advanced micro devices, inc., Shaizeen Dilawarhusen Aga of Santa Clara CA US for advanced micro devices, inc.
IPC Code(s): G06F17/14, G06F7/48, G06F13/16
CPC Code(s): G06F17/142
Abstract: fast fourier transforms for processing-in-memory are described. in accordance with the described techniques, a computing device includes a memory, a host processing unit, and a processing-in-memory unit that operates on data of one or more banks of the memory. the host processing unit stores interacting elements of a fast fourier transform at locations in the one or more banks. the locations are mapped to a lane of the processing-in-memory unit. the host processing unit issues processing-in-memory commands instructing the processing-in-memory unit to load the interacting elements from the locations into the lane of the processing-in-memory unit, and execute an operation on the interacting elements.
Inventor(s): Ashish Jain of Austin TX US for advanced micro devices, inc., Lakshminarayana Pappu of Folsom CA US for advanced micro devices, inc.
IPC Code(s): G06F30/373
CPC Code(s): G06F30/373
Abstract: an apparatus and method for efficiently managing performance and power consumption among replicated functional blocks of an integrated circuit despite different circuit behavior amongst the functional blocks due to manufacturing variations. an integrated circuit includes multiple replicated functional blocks, each being a semiconductor die with a corresponding communication fabric for routing packets. a second functional block placed between a first functional block and a third functional block routes packets to destinations from at least the first and the third functional blocks, and provides higher performance than the first and the third functional blocks due to semiconductor manufacturing variations. a power manager assigns a single power supply voltage to the replicated functional blocks, and assigns a target clock frequency to the first and the third functional blocks. the power manager assigns another clock frequency greater than the target clock frequency to the second functional block.
Inventor(s): Karthik Ramu Sangaiah of Bellevue WA US for advanced micro devices, inc., Yao Cui Fehlis of Austin TX US for advanced micro devices, inc.
IPC Code(s): G06N3/045, G06N3/063
CPC Code(s): G06N3/045
Abstract: disclosed is a computer-implemented method for model ensemble acceleration in an active learning loop. the method includes receiving a set of datapoint inputs, where each datapoint input is an unlabeled equivalent of other datapoint inputs in the set of datapoint inputs and has a different applied weight value. the method then executes a set of neural network models, where the execution of each neural network model is based on the received set of datapoint inputs. the outputs from the set of neural network models are analyzed, where an inference computation is performed, and a label for the set of datapoints is determined. the method then stores the labeled set of datapoint inputs in a database. various other methods, systems, and computer-readable media are also disclosed.
Inventor(s): Rodrigo Andres Urra of Powell OH US for advanced micro devices, inc., David Elias Donaldson of Nevada City CA US for advanced micro devices, inc.
IPC Code(s): G06T1/20, G06T1/60
CPC Code(s): G06T1/20
Abstract: to help enable the faster translation of identifiers during the replay of a captured workload, a processor is configured to generate and insert one or more translation commands into the captured workload. to this end, the processor includes one or more processor cores configured to capture a workload that includes graphics calls referencing an identifier stored in a memory object of a processing unit. based on the graphics calls referencing the identifier stored in a memory object of a processing unit, the processor cores generate a translation command that includes instructions configured to translate the identifier stored in a memory object of a processing unit to a runtime identifier. after generating the translation command, the processor cores then insert the generated translation command in the captured workload at a location based on the graphics calls referencing the identifier.
Inventor(s): Alexander Fuad Ashkar of Winter Park FL US for advanced micro devices, inc., Guennadi Riguer of Markham CA for advanced micro devices, inc., Nishank Pathak of Orlando FL US for advanced micro devices, inc.
IPC Code(s): G06T1/20
CPC Code(s): G06T1/20
Abstract: a processing system includes two or more graphics cores each disposed on respective dies and configured for concurrent processing of command packets. to this end, the processing system is configured to determine two or more command partitions associated with a command packet and to assign each command partition to a graphics core. each graphics core then executes the same command packet by only performing instructions of the command packet associated with the command partitions assigned to the graphics core. further, after executing an instructions of the command packet based on one or more assigned partitions, each graphics core adjusts one or more counters used to synchronize the execution of the command packet across the graphics cores.
20250111469. SMART ACCESS STREAMING_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): Paul Blinzer of Bellevue WA US for advanced micro devices, inc., David Livingstain Ziman of McKinney TX US for advanced micro devices, inc.
IPC Code(s): G06T1/60, G06T15/00, G06T15/04
CPC Code(s): G06T1/60
Abstract: systems, apparatuses, and methods for rendering textures by prefetching texture data are disclosed. source texture data is identified based at least in part on one or more programmable instructions. a prefetch of the source texture data is caused based on level of details associated with the source texture data. further, a list data blocks of the source texture data and a mapping between each data block and corresponding allocated memory address space allocated to each data block on the memory device is maintained. responsive to a request to load a given data block, the given data block from the memory device is loaded using the list.
Inventor(s): Karthik Mohan Kumar of San Jose CA US for advanced micro devices, inc., Archana Ramalingam of Bellevue WA US for advanced micro devices, inc., Michael Mantor of Orlando FL US for advanced micro devices, inc., Pedro Antonio Pena of Orlando FL US for advanced micro devices, inc.
IPC Code(s): G06T15/00, G06T15/04, G10L13/02
CPC Code(s): G06T15/005
Abstract: methods and systems are provided for generating a stylized representation of a non-player character (npc) in a virtual environment. a multimodal plurality of inputs regarding characteristics of the npc is received, which is processed to generate visual data representing the npc's appearance and to generate behavior data representing the npc's actions. the generated visual data and behavior data are adapted to a selected character model to create an adapted configuration model, which is used to generate rendering information for the npc.
Inventor(s): Boris Ivanovic of Markham CA for advanced micro devices, inc., Guennadi Riguer of Markham CA for advanced micro devices, inc., Michal Adam Wozniak of Santa Clara CA US for advanced micro devices, inc.
IPC Code(s): G06T15/04, G06T15/00
CPC Code(s): G06T15/04
Abstract: a technique for rendering is provided. the technique includes determining a level of detail for a shade space texture and a screen space; shading the shade space texture having a resolution based on the level of detail; and for a reconstruction operation, performing sampling from the shade space texture, the sampling including a high frequency attenuation of samples of the shade space texture.
Inventor(s): Leo Hendrik Reyes Lozano of Bellevue WA US for advanced micro devices, inc.
IPC Code(s): G06T15/06, G06T15/08
CPC Code(s): G06T15/06
Abstract: a technique for building a bounding volume hierarchy is disclosed. the technique includes for a subject node, selecting a dimension along which to perform a split to form child nodes of the subject node; assigning primitives of the subject node to the child nodes; and updating bounds for the child nodes in a next split dimension and not in the other dimensions.
Inventor(s): Michael John Livesley of Milton Keynes GB for advanced micro devices, inc., David William John Pankratz of Markham CA for advanced micro devices, inc., Sean Keely of Austin TX US for advanced micro devices, inc., Andrew Erin Kensler of Bellevue WA US for advanced micro devices, inc.
IPC Code(s): G06T15/06, G06T17/00
CPC Code(s): G06T15/06
Abstract: a technique for performing ray tracing operations is provided. the technique includes for a ray being tested for intersection with geometry associated with a bounding volume hierarchy, traversing to a pre-filtering node that includes information for filtering out triangles of a leaf node of the bounding volume hierarchy; evaluating a quantized ray that corresponds to the ray against quantized triangles of the pre-filtering node to filter out one or more triangles of the leaf node from consideration; and testing the triangles of the leaf node that are not filtered out and not testing the triangles of the leaf node that are filtered out.
Inventor(s): Andrew Erin Kensler of Bellevue WA US for advanced micro devices, inc., Sean Keely of Austin TX US for advanced micro devices, inc., Michael John Livesley of Milton Keynes GB for advanced micro devices, inc., David William John Pankratz of Markham CA for advanced micro devices, inc.
IPC Code(s): G06T15/06, G06T17/00
CPC Code(s): G06T15/06
Abstract: devices and methods for rendering objects using ray tracing are provided which include during a build time: generating an accelerated hierarchy structure comprising data representing an approximate volume bounding a group of geometric shapes representing the objects in the scene and data representing the geometric shapes; and generating additional data used to transform rays, to be cast in the scene, from a high precision space to a low precision space; and during a render time occurring after the build time: performing ray intersection tests, using the additional data generated during the build time, for the rays in the scene; and rendering the scene based on the ray intersection tests. because the additional data is generated prior to render time, the additional data can be used to perform the ray intersection testing more efficiently.
20250111598. HYBRID DEFERRED DECOUPLED RENDERING_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): Michal Adam Wozniak of Santa Clara CA US for advanced micro devices, inc., Guennadi Riguer of Markham CA for advanced micro devices, inc.
IPC Code(s): G06T15/80, G06T15/04
CPC Code(s): G06T15/80
Abstract: a technique for rendering is provided. the technique includes performing a visibility operation to generate shade space visibility information and reconstruction information; performing a shade space shading operation based on the shade space visibility information generate shaded shade space textures; and performing a reconstruction operation based on the reconstruction information and the shaded shade space textures.
Inventor(s): Guennadi Riguer of Markham CA for advanced micro devices, inc., Michal Adam Wozniak of Santa Clara CA US for advanced micro devices, inc.
IPC Code(s): G06T15/80, G06T17/20
CPC Code(s): G06T15/80
Abstract: a technique for rendering is provided. the technique includes performing a visibility pass that designates portions of shade space textures visible in a scene, wherein the visibility pass generates tiles that cover the shade space textures visible in the scene; performing a temporal rate controller operation; performing a shade space shading operation on the tiles that cover the shade space textures visible in the scene based on a temporal shading rate output by the temporal rate controller operation, wherein only a subset of samples in the tiles that cover the shade space textures visible in the scene are shaded in the shade space shading operation; and performing a reconstruction operation using output from the shade space shading operation to produce a final scene.
Inventor(s): Guennadi Riguer of Markham CA US for advanced micro devices, inc., Michal Adam Wozniak of Santa Clara CA US for advanced micro devices, inc.
IPC Code(s): G06T15/80, G06T17/20
CPC Code(s): G06T15/80
Abstract: a technique for rendering is provided. the technique includes performing a visibility pass that designates portions of shade space textures visible in a scene, wherein the visibility pass generates tiles that cover shade space textures visible in the scene; performing a rate controller operation on output of the visibility pass using spatially-adaptive sampling; performing a sparse shade space shading operation on the tiles that cover the shade space textures visible in the scene based on a result of the spatially-adaptive sampling; performing a regularization operation based on an output of the sparse shade space shading operation; and performing a reconstruction operation using output from the regularization operation to produce a final scene.
Inventor(s): Guennadi Riguer of Markham CA for advanced micro devices, inc., Michal Adam Wozniak of Santa Clara CA US for advanced micro devices, inc.
IPC Code(s): G06T15/80
CPC Code(s): G06T15/80
Abstract: a technique for rendering is provided. the technique includes performing a visibility pass that designates portions of shade space textures visible in a scene, wherein the visibility pass generates tiles that cover shade space textures visible in the scene; performing a rate controller operation on output of the visibility pass using spatiotemporal adaptive sampling; performing a shade space shading operation on the tiles that cover the shade space textures visible in the scene based on a result of the spatiotemporal adaptive sampling; performing a regularization operation based on an output of the shade space shading operation; and performing a reconstruction operation using output from the regularization operation to produce a final scene.
Inventor(s): Chandra Sekhar Mandalapu of Ft. Collins CO US for advanced micro devices, inc., Raja Swaminathan of Austin TX US for advanced micro devices, inc., Liwei Wang of Austin TX US for advanced micro devices, inc., John Wuu of Ft. Collins CO US for advanced micro devices, inc.
IPC Code(s): H01L21/20, H01L21/683, H01L23/00
CPC Code(s): H01L21/2007
Abstract: a hybrid bonding method includes fabricating plural semiconductor devices in a region of a bottom wafer adjacent to a front surface thereof, fusion bonding the front surface to a carrier substrate, thinning the bottom wafer opposite to the front surface to expose conductive regions of the semiconductor devices, forming a dielectric layer over a backside of the semiconductor devices, forming openings in the dielectric layer to expose the conductive regions, forming metal pads within the openings, dicing the bottom wafer and the carrier substrate to singulate the plural semiconductor devices, bonding the dielectric layer overlying the backside of the semiconductor devices to a dielectric layer overlying a front surface of a top wafer, bonding the metal pads within the openings in the dielectric layer to metal pads overlying the front surface of the top wafer, and removing the carrier substrate from the front surface of the bottom wafer.
Inventor(s): Sriram Chandrasekaran of Austin TX US for advanced micro devices, inc., Hemanth Kumar Dhavaleswarapu of Austin TX US for advanced micro devices, inc., Robert Grant Spurney of Austin TX US for advanced micro devices, inc.
IPC Code(s): H01L23/373, H01L23/00, H01L23/367, H01L23/498
CPC Code(s): H01L23/3735
Abstract: a method can include embedding one or more thermal sources in a semiconductor package substrate and positioning one or more substrate buildup layers above the one or more thermal sources. the method can also include forming one or more thermal vias in the one or more substrate buildup layers. various other methods and systems are also disclosed.
Inventor(s): HaiFeng Gu of Shanghai CN for advanced micro devices, inc.
IPC Code(s): H01R12/71, H01R12/70, H01R12/77
CPC Code(s): H01R12/716
Abstract: a data interface connector and method of manufacture and/or assembly thereof can include first electrical terminals at a first end of the data interface connector, the first electrical terminals being configured to interface with a mating data interface connector conforming to a first data interface specification. the data interface connector and method of manufacture and/or assembly thereof can include second electrical terminals at a second end of the data interface connector, the second electrical terminals being configured to interface with data interface pads on a circuit board; where the data interface pads have pitches and lengths according to a second data interface specification.
Inventor(s): David King Wai Li of Austin TX US for advanced micro devices, inc., Indrani Paul of Austin TX US for advanced micro devices, inc.
IPC Code(s): H02J4/00, G01R19/165
CPC Code(s): H02J4/00
Abstract: the disclosed device includes power circuits that can communicate with a control circuit. in response to a power circuit communicating a low efficiency state, the control circuit can redistribute at least a portion of a load of the power circuit to one or more other power circuits. various other methods, systems, and computer-readable media are also disclosed.
Inventor(s): Wei Han of Shangahi CN for advanced micro devices, inc., Meeta Surendramohan Srivastav of Austin TX US for advanced micro devices, inc., LiLi Chen of Shanghai CN for advanced micro devices, inc., Indrani Paul of Austin TX US for advanced micro devices, inc.
IPC Code(s): H03M1/36, H03M1/16, H04Q9/00
CPC Code(s): H03M1/36
Abstract: an apparatus can include: a processor; a voltage regulator configured to provide a processor voltage and a processor current to the processor; and a voltage regulator controller that can include a current sensor comprising an analog-to-digital converter (adc) having an adc input range and configured to provide current data based on an adc input voltage, and a configuration manager configured to receive processor power data and adjust the adc input range based on the processor power data. various other methods, systems, and computer-readable media are also disclosed.
Inventor(s): Carl Kittredge Wakeland of Santa Clara CA US for advanced micro devices, inc., Uma Sankara Rao Balla of Hyderabad IN for advanced micro devices, inc.
IPC Code(s): H04S3/00, G06F3/16
CPC Code(s): H04S3/008
Abstract: a processing system includes a hardware synchronizer to synchronize the transmission of audio data from multiple i2s controllers of a processing system to one or more audio codecs. in some embodiments, each of the i2s controllers receives audio data from one or more audio data sources and stores the audio data at a buffer associated with the controller. the hardware synchronizer initiates synchronized transmission of the audio data from the plurality of controllers to the one or more codecs in response to the buffer associated with each controller being filled to a predetermined level. in some embodiments, until the controllers begin transmission of the audio data, the controllers transmit mute (null) data to the one or more codecs such that the one or more codecs receives a frame start followed by null data for each frame.
Advanced Micro Devices, Inc. patent applications on April 3rd, 2025
- Advanced Micro Devices, Inc.
- G06F1/08
- G06F21/64
- G06F21/73
- H01L23/525
- CPC G06F1/08
- Advanced micro devices, inc.
- G06F1/3203
- CPC G06F1/3203
- G06F3/06
- CPC G06F3/0622
- G11C11/22
- H10B53/30
- CPC G06F3/0652
- CPC G06F3/0658
- CPC G06F3/0659
- G06F9/48
- G06F1/3296
- CPC G06F9/4831
- G06F9/54
- CPC G06F9/4881
- G06F9/50
- CPC G06F9/5033
- G06F11/07
- G06F11/10
- CPC G06F11/0772
- G06F12/02
- CPC G06F12/023
- G06F13/16
- G11C11/4076
- G06F12/0811
- CPC G06F12/0811
- G06F12/1027
- G06F12/0815
- CPC G06F12/0815
- G06F12/0891
- G06F12/0877
- CPC G06F12/0891
- G06F12/0897
- CPC G06F12/0897
- G06F12/10
- CPC G06F12/10
- G06F12/0873
- CPC G06F12/1027
- G06F12/1045
- CPC G06F12/1045
- G06F12/122
- CPC G06F12/122
- G06F13/42
- CPC G06F13/1668
- G06N3/08
- G06F13/40
- G06F12/06
- CPC G06F13/404
- G06F17/14
- G06F7/48
- CPC G06F17/142
- G06F30/373
- CPC G06F30/373
- G06N3/045
- G06N3/063
- CPC G06N3/045
- G06T1/20
- G06T1/60
- CPC G06T1/20
- G06T15/00
- G06T15/04
- CPC G06T1/60
- G10L13/02
- CPC G06T15/005
- CPC G06T15/04
- G06T15/06
- G06T15/08
- CPC G06T15/06
- G06T17/00
- G06T15/80
- CPC G06T15/80
- G06T17/20
- H01L21/20
- H01L21/683
- H01L23/00
- CPC H01L21/2007
- H01L23/373
- H01L23/367
- H01L23/498
- CPC H01L23/3735
- H01R12/71
- H01R12/70
- H01R12/77
- CPC H01R12/716
- H02J4/00
- G01R19/165
- CPC H02J4/00
- H03M1/36
- H03M1/16
- H04Q9/00
- CPC H03M1/36
- H04S3/00
- G06F3/16
- CPC H04S3/008