TEXAS INSTRUMENTS INCORPORATED patent applications on March 27th, 2025
Patent Applications by TEXAS INSTRUMENTS INCORPORATED on March 27th, 2025
TEXAS INSTRUMENTS INCORPORATED: 27 patent applications
TEXAS INSTRUMENTS INCORPORATED has applied for patents in the areas of H01L23/00 (3), H01L21/56 (3), G06F9/38 (3), H01L23/31 (3), H01L23/495 (3) G01R31/31723 (1), H02J7/00712 (1), H04W76/12 (1), H04N13/398 (1), H04N9/3188 (1)
With keywords such as: circuit, terminal, coupled, input, control, output, layer, voltage, current, and cache in patent application abstracts.
Patent Applications by TEXAS INSTRUMENTS INCORPORATED
20250102569. 3D TAP & SCAN PORT ARCHITECTURES_simplified_abstract_(texas instruments incorporated)
Inventor(s): Lee D. Whetsel of Parker TX US for texas instruments incorporated
IPC Code(s): G01R31/317, G01R31/28, G01R31/3177, G01R31/3183, G01R31/3185
CPC Code(s): G01R31/31723
Abstract: this disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. the die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.
20250102587. EXCITATION FOR SPECTROSCOPY_simplified_abstract_(texas instruments incorporated)
Inventor(s): Bassem IBRAHIM of Allen TX US for texas instruments incorporated, Branko MAJMUNOVIC of Dallas TX US for texas instruments incorporated, David P MAGEE of Allen TX US for texas instruments incorporated
IPC Code(s): G01R31/389, G01R31/367, G01R31/3842
CPC Code(s): G01R31/389
Abstract: an apparatus includes a charge transfer circuit, a control circuit, and a processing circuit. the charge transfer circuit has a first terminal, a second terminal, a third terminal, and a control input. the control circuit has a control output coupled to the control input. the processing circuit has a first input, a second input, and an output. the processing circuit is configured to receive a first signal at the first input and receive a second signal at the second input. the first signal represents a current through the charge transfer circuit. the second signal represents at least one of a first voltage between the first and second terminals or a second voltage between the second and third terminals. the processing circuit is also configured to provide a third signal based on the first and second signals at the output.
Inventor(s): Rinu Mathew of Bangalore IN for texas instruments incorporated, Venkatesh Kadlimatti of Bangalore IN for texas instruments incorporated, Harikrishna Parthasarathy of Bangalore IN for texas instruments incorporated
IPC Code(s): G05F1/575, G05F3/26, H02M1/00
CPC Code(s): G05F1/575
Abstract: a power supply system may include multiple dc-to-dc (direct current) voltage regulators coupled in parallel to a load, and control circuitry to control the parallel-operating regulators. the control circuitry may include a first share control circuit, a second share control circuit, and a voltage regulation circuit. the first and second share control circuits may operate together with the voltage regulation circuit to control, respectively, the parallel-operating regulators to regulate a common output voltage. additionally, first and second share control circuits may operate together with the voltage regulation circuit to control respective share of the load current by the parallel-operating regulators.
Inventor(s): Vignesh Raghavendra of Bengaluru IN for texas instruments incorporated, Sriramakrishnan Govindarajan of Bengaluru IN for texas instruments incorporated, Mihir Narendra Mody of Bengaluru IN for texas instruments incorporated, Sai Karthik Rajaraman of Frisco TX US for texas instruments incorporated, Shailesh Ganapat Ghotgalkar of Bengaluru IN for texas instruments incorporated, Mohammad Asif Farooqui of Bengaluru IN for texas instruments incorporated
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: an example apparatus includes a read queue to store a first read request to access a first storage, sequencing circuitry coupled to the read queue, and prioritization circuitry coupled to the sequencing circuitry and coupled to the first storage and a second storage via a shared bus. the example sequencing circuitry is to sequence a portion of a second request to access the second storage to be interleaved with a wait interval of the first read request, the second request queued after the first read request. additionally, the example prioritization circuitry is to generate a first transaction to access the first storage over the shared bus and a second transaction to access the second storage over the shared bus concurrently with the first transaction, the first transaction based on the first read request, the second transaction based on the second request.
Inventor(s): Yaron ALPERT of Hod Hasharon IL for texas instruments incorporated, Alon SREDNIZKI of Gedera IL for texas instruments incorporated
IPC Code(s): G06F11/30, G06F1/3203, G06F11/34
CPC Code(s): G06F11/3062
Abstract: a processor in a device is configured to access a power policy for the device, where the power policy indicates a relationship between power consumption by the device and another performance variable of the device. the processor is also configured to produce an operating point for the device based at least in part on the power policy. the processor is also configured to provide information regarding the operating point to a management entity that manages the device.
Inventor(s): Abhijeet Ashok Chachad of Plano TX US for texas instruments incorporated, Timothy Anderson of University Park TX US for texas instruments incorporated, Kai Chirca of Dallas TX US for texas instruments incorporated, David Matthew Thompson of Dallas TX US for texas instruments incorporated
IPC Code(s): G06F12/0842, G06F1/14, G06F9/38, G06F9/54, G06F12/0811, G06F12/0888
CPC Code(s): G06F12/0842
Abstract: in described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. the higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. the higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.
20250103503. ZERO LATENCY PREFETCHING IN CACHES_simplified_abstract_(texas instruments incorporated)
Inventor(s): Oluleye Olorode of Garland TX US for texas instruments incorporated, Ramakrishnan Venkatasubramanian of Plano TX US for texas instruments incorporated, Hung Ong of Plano TX US for texas instruments incorporated
IPC Code(s): G06F12/0862, G06F9/30, G06F9/38, G06F12/0811, G06F12/0815, G06F12/0875, G06F12/0888, G06F12/1027
CPC Code(s): G06F12/0862
Abstract: this invention involves a cache system in a digital data processing apparatus including: a central processing unit core; a level one instruction cache; and a level two cache. the cache lines in the second level cache are twice the size of the cache lines in the first level instruction cache. the central processing unit core requests additional instructions when needed via a request address. upon a miss in the level one instruction cache that causes a hit in the upper half of a level two cache line, the level two cache supplies the upper half level cache line to the level one instruction cache. on a following level two cache memory cycle, the level two cache supplies the lower half of the cache line to the level one instruction cache. this cache technique thus prefetchs the lower half level two cache line employing fewer resources than an ordinary prefetch.
Inventor(s): Duc Quang Bui of Grand Prairie TX US for texas instruments incorporated, Joseph Raymond Michael Zbiciak of Alviso CA US for texas instruments incorporated
IPC Code(s): G06F12/1045, G06F7/24, G06F7/487, G06F7/499, G06F7/53, G06F7/57, G06F9/30, G06F9/32, G06F9/345, G06F9/38, G06F9/48, G06F11/00, G06F11/10, G06F12/0862, G06F12/0875, G06F12/0897, G06F12/1009, G06F15/78, G06F17/16, H03H17/06
CPC Code(s): G06F12/1045
Abstract: in a method of operating a computer system, an instruction loop is executed by a processor in which each iteration of the instruction loop accesses a current data vector and an associated current vector predicate. the instruction loop is repeated when the current vector predicate indicates the current data vector contains at least one valid data element and the instruction loop is exited when the current vector predicate indicates the current data vector contains no valid data elements.
Inventor(s): Sudhakar SURENDRAN of Bengaluru IN for texas instruments incorporated, Venkatraman RAMAKRISHNAN of Bengaluru IN for texas instruments incorporated
IPC Code(s): G06F30/398, G06F30/3312
CPC Code(s): G06F30/398
Abstract: a technique for convergence verification including receiving a data object representation of a first circuit block, receiving one or more assumptions associated with the first circuit block, identifying a synchronization scheme coupled to a port of the first circuit block, determining that the synchronization scheme is within a threshold flip-flop depth, identifying, based on the determination that the synchronization scheme is within the threshold flip-flop depth, a type of the synchronization scheme and a flip-flop depth between the synchronization scheme and the port, generating first convergence information for the first circuit block based on the identified type and flip-flop depth of the synchronization scheme, and outputting the generated convergence information.
Inventor(s): Jesus Bajo Bautista, JR. of Baguio City PH for texas instruments incorporated, Jeffrey Dorado Emperador of Baguio City PH for texas instruments incorporated, Francis Masiglat de Vera of Baguio City PH for texas instruments incorporated
IPC Code(s): H01L23/31, H01L21/48, H01L21/56, H01L23/00, H01L23/495, H01L23/498
CPC Code(s): H01L23/315
Abstract: integrated circuit packaging with cavities and methods of manufacturing the same are disclosed. an example apparatus includes a semiconductor die and a housing enclosing portions of the semiconductor die. the housing defines an opening that extends from a surface of the semiconductor die to an external environment, the housing formed of a first material. the example apparatus includes a second material disposed within the opening to block exposure of the semiconductor die to the external environment.
Inventor(s): Li Jiang of Allen TX US for texas instruments incorporated, Rey Javier of Plano TX US for texas instruments incorporated, Guangxu Li of Allen TX US for texas instruments incorporated, Enis Tuncer of Dallas TX US for texas instruments incorporated
IPC Code(s): H01L23/495, H01L21/56, H01L23/00, H01L23/31
CPC Code(s): H01L23/49541
Abstract: an electronic device includes a package structure having four lateral corners, a semiconductor die at least partially enclosed inside the package structure and attached to a die attach pad, conductive leads at least partially exposed outside the package structure along the four lateral sides, a first one of the conductive leads electrically connected to the semiconductor die, an instance of a first conductive feature partially exposed outside the package structure at each of the corners, and an instance of a second conductive feature partially exposed outside the package structure and contacting a respective instance of the first conductive feature at each of the corners, the instance of the second conductive feature exposed outside the package structure along the first side.
20250105135. CORRUGATED CAPACITOR_simplified_abstract_(texas instruments incorporated)
Inventor(s): Jonas Höhenberger of Kissing DE for texas instruments incorporated, Michael Hans Enzelberger-Heim of Munich DE for texas instruments incorporated
IPC Code(s): H01L23/522, H01L27/06
CPC Code(s): H01L23/5223
Abstract: the present disclosure generally relates to a corrugated capacitor in an integrated circuit (ic). in an example, an ic includes a first corrugated conductive layer, a second corrugated conductive layer, and a corrugated dielectric layer. the first corrugated conductive layer and the second corrugated conductive layer are over a semiconductor substrate. the corrugated dielectric layer is between the first corrugated conductive layer and the second corrugated conductive layer. various examples may achieve a larger surface areas for respective plates of a capacitor for a given lateral footprint of the capacitor.
Inventor(s): JOHN CARLO MOLINA of LIMAY PH for texas instruments incorporated, RAFAEL JOSE LIZARES GUEVARA of Makati Metro Manila PH for texas instruments incorporated
IPC Code(s): H01L23/00, H01L21/56, H01L23/31, H01L23/495
CPC Code(s): H01L24/29
Abstract: one example includes an electronic circuit package. the electronic circuit package includes a lead frame. the electronic circuit package includes an electronic circuit die disposed on the lead frame. the electronic circuit package includes a metal plate structure formed on the electronic circuit die, the metal plate structure comprising an aperture that extends through the metal plate structure from a first surface coupled to the electronic circuit die to a second surface opposite the first surface, and further comprising a tapered foot portion formed around a periphery of the metal plate structure at the first surface. the electronic circuit package includes a molding material covering the electronic circuit die around the metal plate structure.
Inventor(s): Baher S. Haroun of Allen TX US for texas instruments incorporated
IPC Code(s): H01P3/16, G01S7/03, G01S13/931, H01Q1/32
CPC Code(s): H01P3/16
Abstract: radar systems are provided for transmitting radar signals using one or more flexible dielectric waveguides (dwgs), each having a core member surrounded by a cladding, in which the core and cladding have different dielectric constants. a single radar circuit may be used to generate radar signals that are distributed, via the dwgs, to multiple launch structures placed at various locations on a vehicle. in an example, a launch structure, coupled to a port of the radar circuit, has an outer surface that is configured to couple to an inner surface of a body part of an external structure to emit a radar signal through the outer surface in a path that extends through the body part, in which the body part is non-transparent to light and does not have an opening in the path of the radar signal.
Inventor(s): Chutao Zhang of Shenzhen CN for texas instruments incorporated
IPC Code(s): H02J7/00, G01R31/3842
CPC Code(s): H02J7/00712
Abstract: a method includes detecting a voltage of the battery, detecting a current of the battery, determining a depth of discharge of the battery based on the voltage and the current of the battery, and controlling terminating charging of the battery responsive to the determined depth of discharge of the battery reaching a depth of discharge threshold. a system includes a battery gauge circuit and a processor coupled to the battery gauge circuit. the battery gauge circuit has a voltage sense input and a current sense input and is configured to determine a depth of discharge of a battery based on a battery voltage at the voltage sense input and a battery current at the current sense input. the processor is configured to control terminating charging of the battery responsive to the determined depth of discharge reaching a depth of discharge threshold.
Inventor(s): Jian LIANG of Shanghai CN for texas instruments incorporated, Yao LU of Shanghai CN for texas instruments incorporated, Chen FENG of Shanghai CN for texas instruments incorporated
IPC Code(s): H02M3/155
CPC Code(s): H02M3/155
Abstract: a circuit includes a comparator circuit having a first input, a second input, a first output and a second output. the circuit also includes the first input configured to receive an input voltage of a power supply circuit and the second input configured to receive an output voltage of the power supply circuit. additionally, the circuit includes the first output to provide the larger of the input voltage or the output voltage and the second output to provide a logic low signal responsive to the input voltage being less than the output voltage, and to provide a logic high signal responsive to the input voltage being greater than or equal to the output voltage.
Inventor(s): Rengang CHEN of Bethlehem PA US for texas instruments incorporated, Bo WANG of Easton PA US for texas instruments incorporated, Evan REUTZEL of Center Valley PA US for texas instruments incorporated, Dattatreya Baragur SURYANARAYANA of Bengaluru IN for texas instruments incorporated, Bhaskar RAMACHANDRAN of Bengaluru IN for texas instruments incorporated, Preetam TADEPARTHY of Bengaluru IN for texas instruments incorporated
IPC Code(s): H02M3/158, H02M1/00
CPC Code(s): H02M3/158
Abstract: a circuit includes a current emulation circuit having an output and a current measurement circuit having an input and an output. the circuit also includes a first switch having a first terminal and a second terminal, the first terminal coupled to the output of the current measurement circuit and a second switch having a first terminal and a second terminal, the first terminal coupled to the output of the current emulation circuit and the second terminal coupled to the second terminal of the first switch. additionally, the circuit includes a third switch having a first terminal and a second terminal, the first terminal coupled to the first terminal of the first switch and the second terminal coupled to the first terminal of the second switch.
Inventor(s): Hua Shao of Tucson AZ US for texas instruments incorporated, Paul Damitio of Tucson AZ US for texas instruments incorporated, Bharath Karthik Vasan of Tucson AZ US for texas instruments incorporated, Joel M. Halbert of Tucson AZ US for texas instruments incorporated
IPC Code(s): H03F3/04
CPC Code(s): H03F3/04
Abstract: an example apparatus includes: first buffer circuitry having a first terminal and a second terminal; second buffer circuitry having a first terminal and a second terminal; third buffer circuitry having a first terminal and a second terminal, the first terminal of the third buffer circuitry coupled to the first terminal of the second buffer circuitry; a first transistor having a first terminal, a second terminal and a control terminal, the first terminal of the first transistor coupled to the first terminal of the first buffer circuitry, the control terminal of the first transistor coupled to the second terminal of the second buffer circuitry; a second transistor having a first terminal and a second terminal, the first terminal of the second transistor coupled to the second terminal of the first buffer circuitry.
Inventor(s): Hua Shao of Tucson AZ US for texas instruments incorporated, Paul Damitio of Tucson AZ US for texas instruments incorporated, Bharath Karthik Vasan of Tucson AZ US for texas instruments incorporated, Joel Martin Halbert of Tucson AZ US for texas instruments incorporated
IPC Code(s): H03F3/45, H03F1/30, H03K17/30
CPC Code(s): H03F3/45165
Abstract: an amplifier includes first through sixth transistors. the first transistor is of a first polarity type and has a control terminal and first and second terminals. the second transistor is of a second polarity type and has a control terminal and first and second terminals. the third transistor is of the first polarity type and has a control terminal and first and second terminals. the second terminal of the third transistor is coupled to the first terminal of the second transistor. the fourth transistor is of the second polarity type and has a control terminal and first and second terminals. the first terminal of the fourth transistor is coupled to the second terminal of the second transistor. the fifth transistor has a control terminal coupled to the control terminal of the third transistor. a sixth transistor has a control terminal coupled to the control terminal of the fourth transistor.
20250105839. GATE VOLTAGE DETECTOR_simplified_abstract_(texas instruments incorporated)
Inventor(s): Xiaochun Zhao of Allen TX US for texas instruments incorporated
IPC Code(s): H03K17/687, G01R19/00, H03K19/20
CPC Code(s): H03K17/6871
Abstract: an apparatus includes a circuit including a circuit input, a circuit output, and a circuit terminal. a current mirror has a mirror input and a mirror output. the mirror input is coupled to the circuit terminal. a logic gate has a logic gate input coupled to the mirror output. a resistor is coupled between the mirror output and a supply reference terminal. a transistor has a control input and a current terminal. the control input is coupled to the circuit input. the current terminal is coupled to the circuit output.
Inventor(s): Visvesvaraya Appala Pentakota of Bangalore IN for texas instruments incorporated, Srinivas Kumar Reddy Naru of Bangalore IN for texas instruments incorporated, Chirag Shetty of Bangalore IN for texas instruments incorporated, Eeshan Miglani of Bangalore IN for texas instruments incorporated, Neeraj Shrivastava of Bangalore IN for texas instruments incorporated, Narasimhan Rajagopal of Bangalore IN for texas instruments incorporated, Shagun Dusad of Bangalore IN for texas instruments incorporated
IPC Code(s): H03M1/10
CPC Code(s): H03M1/1038
Abstract: in described examples, a circuit includes a multiplexer. the multiplexer receives an input voltage and a calibration signal. an analog-to-digital converter (adc) is coupled to the multiplexer and generates an output code in response to the calibration signal. a storage circuit is coupled to the adc and stores the input code representative of the calibration signal at an address corresponding to the output code. the stored input code includes an index value and a coarse value.
Inventor(s): Jun Zhang of Shanghai CN for texas instruments incorporated
IPC Code(s): H03M1/18, H03F1/38, H03F3/45, H03G1/00, H03G3/00, H03G3/20, H03M3/00
CPC Code(s): H03M1/185
Abstract: a circuit includes an operational amplifier and a resistor network coupled to an output of the operational amplifier. the resistor network includes a first set of resistors coupled between the output of the operational amplifier and a first node of the resistor network, wherein the resistors of the first set are electrically connected in series with each other, a second set of resistors coupled between the first node and a second node of the resistor network, wherein the resistors of the second set are electrically connected in series with each other and include a first number of resistors, a third set of resistors coupled between the second node and a third node of the resistor network, wherein the third node is coupled to a first voltage, and wherein the resistors of the third set are electrically connected in parallel with each other and include a second number of resistors, and a resistor coupled between the first node and the second node and arranged in parallel with the second set of resistors.
Inventor(s): Kaichien Tsai of Allen TX US for texas instruments incorporated, Arvind Kandhalu Raghu of Plano TX US for texas instruments incorporated, Ramanuja Vedantham of Allen TX US for texas instruments incorporated
IPC Code(s): H04B1/713, H04B1/715, H04B17/26, H04B17/318, H04L1/00, H04L1/20, H04L43/0823, H04L43/16, H04L49/15, H04W4/80, H04W40/22, H04W84/18
CPC Code(s): H04B1/713
Abstract: a method for pseudo channel hopping in a node of a wireless mesh network is provided that includes scanning each channel of a plurality of channels used for packet transmission by the node, wherein each channel is scanned for a scan dwell time associated with the channel, updating statistics for each channel based on packets received by the node during the scanning of the channel, and changing scan dwell times of the plurality of channels periodically based on the statistics.
20250106368. OPTICAL DIAMOND PASSBAND FILTER_simplified_abstract_(texas instruments incorporated)
Inventor(s): Jeffrey Kempf of Dallas TX US for texas instruments incorporated
IPC Code(s): H04N9/31, H03H17/06
CPC Code(s): H04N9/3188
Abstract: methods and apparatus for optical filtering. in one example, a device includes a spatial light modulator having a two-dimensional array of square, rectangular, or diamond pixels, and a controller coupled to the spatial light modulator. the controller can be configured to write image data representing an image to the spatial light modulator to control the spatial light modulator to display the image for a frame period, and during the frame period, spatially reposition the image on the array of pixels over a plurality of positions, each individual position of the plurality of positions being maintained for a respective time period, wherein the respective time period is selected according to one or more non-negative coefficients of an anti-aliasing filter transfer function.
Inventor(s): Alexander Lyubarsky of Dallas TX US for texas instruments incorporated, Kristofer Scott Oberascher of Princeton TX US for texas instruments incorporated, Samuel Edward Martin of Plano TX US for texas instruments incorporated
IPC Code(s): H04N13/398, H04N9/31, H04N13/302, H04N13/32, H04N13/361, H04N13/363, H04N13/383
CPC Code(s): H04N13/398
Abstract: a method includes projecting, by a first projector, a first image to a first region, the first image having a first angular resolution and a first number of views. the method also includes projecting, by a second projector, a second image to a second region, the second image having a second angular resolution and a second number of views, where the second region is within the first region, the second angular resolution is greater than the first angular resolution, and the second number of views is greater than the first number of views.
Inventor(s): Leonardo William Estevez of Rockwall TX US for texas instruments incorporated, Ariton Xhafa of Plano TX US for texas instruments incorporated, Ramanuja Vedantham of Allen TX US for texas instruments incorporated, Yanjun Sun of San Diego CA US for texas instruments incorporated
IPC Code(s): H04W76/12, H04W76/14, H04W84/12, H04W88/08
CPC Code(s): H04W76/12
Abstract: an emulated wireless access point (ap) at a first pmc device (pmc1) establishes a first tunneled direct link setup (tdls) session between a first station module (sta1) incorporated into the pmc1 and a second station module (sta2) incorporated into a second pmc device (pmc2). following establishment of the tdls session, the wireless ap is allowed to sleep; and most infrastructure management duties are handled by the sta1 during the session. pmc device battery charge may be conserved as a result. the emulated wireless ap may also establish a second tdls link to a third station module (sta3) incorporated into a third pmc device (pmc3). the sta1 may then bridge data traffic flow between the sta2 and the sta3. such bridging operation may enable communication between two pmc devices otherwise unable to decode data received from the other.
Inventor(s): Sandeep R. Bahl of Palo Alto CA US for texas instruments incorporated, Ujwal Radhakrishna of San Jose CA US for texas instruments incorporated, Chang Soo Suh of Allen TX US for texas instruments incorporated
IPC Code(s): H01L29/778, H01L29/08, H01L29/20, H01L29/66
CPC Code(s): H10D30/475
Abstract: the present disclosure generally relates to a conductive layer in a gate structure of a semiconductor device. the conductive layer may be a silicon layer. an example is a semiconductor device. the semiconductor device includes a channel layer, a barrier layer, a gate layer, and a silicon layer. the channel layer is over a semiconductor substrate. the barrier layer is over the channel layer. the gate layer is over the barrier layer. the silicon layer is over and contacts the gate layer.
TEXAS INSTRUMENTS INCORPORATED patent applications on March 27th, 2025
- TEXAS INSTRUMENTS INCORPORATED
- G01R31/317
- G01R31/28
- G01R31/3177
- G01R31/3183
- G01R31/3185
- CPC G01R31/31723
- Texas instruments incorporated
- G01R31/389
- G01R31/367
- G01R31/3842
- CPC G01R31/389
- G05F1/575
- G05F3/26
- H02M1/00
- CPC G05F1/575
- G06F3/06
- CPC G06F3/0659
- G06F11/30
- G06F1/3203
- G06F11/34
- CPC G06F11/3062
- G06F12/0842
- G06F1/14
- G06F9/38
- G06F9/54
- G06F12/0811
- G06F12/0888
- CPC G06F12/0842
- G06F12/0862
- G06F9/30
- G06F12/0815
- G06F12/0875
- G06F12/1027
- CPC G06F12/0862
- G06F12/1045
- G06F7/24
- G06F7/487
- G06F7/499
- G06F7/53
- G06F7/57
- G06F9/32
- G06F9/345
- G06F9/48
- G06F11/00
- G06F11/10
- G06F12/0897
- G06F12/1009
- G06F15/78
- G06F17/16
- H03H17/06
- CPC G06F12/1045
- G06F30/398
- G06F30/3312
- CPC G06F30/398
- H01L23/31
- H01L21/48
- H01L21/56
- H01L23/00
- H01L23/495
- H01L23/498
- CPC H01L23/315
- CPC H01L23/49541
- H01L23/522
- H01L27/06
- CPC H01L23/5223
- CPC H01L24/29
- H01P3/16
- G01S7/03
- G01S13/931
- H01Q1/32
- CPC H01P3/16
- H02J7/00
- CPC H02J7/00712
- H02M3/155
- CPC H02M3/155
- H02M3/158
- CPC H02M3/158
- H03F3/04
- CPC H03F3/04
- H03F3/45
- H03F1/30
- H03K17/30
- CPC H03F3/45165
- H03K17/687
- G01R19/00
- H03K19/20
- CPC H03K17/6871
- H03M1/10
- CPC H03M1/1038
- H03M1/18
- H03F1/38
- H03G1/00
- H03G3/00
- H03G3/20
- H03M3/00
- CPC H03M1/185
- H04B1/713
- H04B1/715
- H04B17/26
- H04B17/318
- H04L1/00
- H04L1/20
- H04L43/0823
- H04L43/16
- H04L49/15
- H04W4/80
- H04W40/22
- H04W84/18
- CPC H04B1/713
- H04N9/31
- CPC H04N9/3188
- H04N13/398
- H04N13/302
- H04N13/32
- H04N13/361
- H04N13/363
- H04N13/383
- CPC H04N13/398
- H04W76/12
- H04W76/14
- H04W84/12
- H04W88/08
- CPC H04W76/12
- H01L29/778
- H01L29/08
- H01L29/20
- H01L29/66
- CPC H10D30/475
