Intel Corporation patent applications on December 12th, 2024
Patent Applications by Intel Corporation on December 12th, 2024
Intel Corporation: 23 patent applications
Intel Corporation has applied for patents in the areas of H01L23/00 (4), H01L23/498 (4), H01L29/78 (2), H01R12/70 (2), G06F17/16 (2) F04D29/666 (1), H01L23/467 (1), H04L63/12 (1), H04L41/16 (1), H01R12/727 (1)
With keywords such as: device, circuit, semiconductor, integrated, include, frame, apparatus, material, measurement, and electrically in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): Arnab Sen of Whitefield (IN) for intel corporation, Srinivasarao Konakalla of Bangalore (IN) for intel corporation, Samarth Alva of Bangalore (IN) for intel corporation, Amit Kumar of Bangalore (IN) for intel corporation, Rachit Garg of Bangalore (IN) for intel corporation, Bhavaneeswaran Anbalagan of Bangalore (IN) for intel corporation, Raghavendra S. Kanivihalli of Bangalore (IN) for intel corporation, Prasanna Pichumani of Bangalore (IN) for intel corporation
IPC Code(s): F04D29/66, F04D17/16, F04D25/08, F04D29/28, G06F1/20
CPC Code(s): F04D29/666
Abstract: impeller architecture for a cooling fan and methodology for making same. the impeller architecture includes a plurality of blades, individual ones of the blades have a first end that is attached to a hub component in a sequential order, such that sequential first ends are attached to the circumference. an indexing function is applied to the sequential order, and blades or the spaces therebetween are modified accordingly to have a blade type based on their sequential location and the indexing function. the indexing function can be, in a non-limiting example, odd numbers or prime numbers.
Inventor(s): Yuval Amizur of Kfar-Saba (IL) for intel corporation, Ofer Bar-Shalom of Kiryat Ono (IL) for intel corporation, Leor Banin of Petach Tikva (IL) for intel corporation, Nir Dvorecki of Herzeliya (IL) for intel corporation
IPC Code(s): G01S13/76, H04W64/00
CPC Code(s): G01S13/765
Abstract: some demonstrative embodiments include apparatuses systems and/or methods of collaborative time of arrival (ctoa). for example, an apparatus may include circuitry and logic configured to cause a ctoa broadcasting wireless communication station (sta) (bsta) to broadcast an announcement frame to announce a ranging-to-self sequence of a ctoa measurement protocol; to broadcast a first ranging measurement frame of the ranging-to-self sequence subsequent to the announcement frame; to broadcast a second ranging measurement frame of the ranging-to-self sequence subsequent to the first ranging measurement frame; and to broadcast a location measurement report (lmr) frame of the ranging-to-self sequence subsequent to the second ranging measurement frame, the lmr frame including a time of departure (tod) of the first ranging measurement frame.
Inventor(s): Rafael ROSALES of Unterhaching (DE) for intel corporation, Florian GEISSLER of Munich (DE) for intel corporation, Ignacio J. ALVAREZ of Portland OR (US) for intel corporation, Neslihan KOSE CIHANGIR of Munich (DE) for intel corporation
IPC Code(s): G05D1/00, B60W60/00, G01C21/34, G05D1/617
CPC Code(s): G05D1/0214
Abstract: a controller for an autonomous vehicle may include: one or more processors configured to: determine a maneuver planned for the vehicle based on a safety driving model and based on a first message from a network component external to the vehicle, the first message including a respective assessment for each proposed maneuver of at least two maneuvers proposed for the vehicle, and provide an in-vehicle instruction to perform the maneuver planned for the vehicle.
Inventor(s): Daniel Ragland of Sherwood OR (US) for intel corporation, Nadav Shulman of Tel Mond M (IL) for intel corporation, Louis Draghi of Hillsboro OR (US) for intel corporation
IPC Code(s): G06F1/10, G06F1/08, G06F1/20, G06F1/3206, G06F16/9035
CPC Code(s): G06F1/10
Abstract: methods, apparatus, and articles of manufacture to dynamically configure overclocking frequency have been disclosed. an example apparatus include a clock rate adjuster to cause a processor core to operate at a first overclocked clock rate; a comparator to compare a sensed temperature corresponding to the processor core to a threshold; and the clock rate adjuster to, when the sensed temperature satisfies the threshold, decrease a clock rate of the processor core from the first overclocked clock rate by a user-defined amount, the decreased clock rate being above a normal operating clock rate of the processor core.
Inventor(s): William C. Deleeuw of Beaverton OR (US) for intel corporation
IPC Code(s): G06F3/01, G06T13/80, G06V10/143, G06V40/19, G10L15/02, G10L15/22, G10L15/30, G10L21/003
CPC Code(s): G06F3/013
Abstract: technologies for natural language interactions with virtual personal assistant systems include a computing device configured to capture audio input, distort the audio input to produce a number of distorted audio variations, and perform speech recognition on the audio input and the distorted audio variants. the computing device selects a result from a large number of potential speech recognition results based on contextual information. the computing device may measure a user's engagement level by using an eye tracking sensor to determine whether the user is visually focused on an avatar rendered by the virtual personal assistant. the avatar may be rendered in a disengaged state, a ready state, or an engaged state based on the user engagement level. the avatar may be rendered as semitransparent in the disengaged state, and the transparency may be reduced in the ready state or the engaged state. other embodiments are described and claimed.
20240411717. CACHE STRUCTURE AND UTILIZATION_simplified_abstract_(intel corporation)
Inventor(s): Altug Koker of El Dorado Hills CA (US) for intel corporation, Lakshminarayanan Striramassarma of Folsom CA (US) for intel corporation, Aravindh Anantaraman of Folsom CA (US) for intel corporation, Valentin Andrei of San Jose CA (US) for intel corporation, Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, Sean Coleman of Folsom CA (US) for intel corporation, Varghese George of Folsom CA (US) for intel corporation, Pattabhiraman K of Bangalore KA (IN) for intel corporation, Mike MacPherson of Portland OR (US) for intel corporation, Subramaniam Maiyuran of Gold River CA (US) for intel corporation, ElMoustapha Ould-Ahmed-Vall of Chandler AZ (US) for intel corporation, Vasanth Ranganathan of El Dorado Hills CA (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation, Jayakrishna P S of Bangalore KA (IN) for intel corporation, Prasoonkumar Surti of Folsom CA (US) for intel corporation
IPC Code(s): G06F15/78, G06F7/544, G06F7/575, G06F7/58, G06F9/30, G06F9/38, G06F9/50, G06F12/02, G06F12/06, G06F12/0802, G06F12/0804, G06F12/0811, G06F12/0862, G06F12/0866, G06F12/0871, G06F12/0875, G06F12/0882, G06F12/0888, G06F12/0891, G06F12/0893, G06F12/0895, G06F12/0897, G06F12/1009, G06F12/128, G06F15/80, G06F17/16, G06F17/18, G06N3/08, G06T1/20, G06T1/60, G06T15/06, H03M7/46
CPC Code(s): G06F15/7839
Abstract: embodiments are generally directed to cache structure and utilization. an embodiment of an apparatus includes one or more processors including a graphics processor; a memory for storage of data for processing by the one or more processors; and a cache to cache data from the memory; wherein the apparatus is to provide for dynamic overfetching of cache lines for the cache, including receiving a read request and accessing the cache for the requested data, and upon a miss in the cache, overfetching data from memory or a higher level cache in addition to fetching the requested data, wherein the overfetching of data is based at least in part on a current overfetch boundary, and provides for data is to be prefetched extending to the current overfetch boundary.
Inventor(s): Markus SCHWIEGERSHAUSEN of Neubiberg (DE) for intel corporation, Krzysztof DOMANSKI of Neubiberg (DE) for intel corporation
IPC Code(s): G06F30/398, G06F30/31, G06F30/392
CPC Code(s): G06F30/398
Abstract: a method to manufacture an integrated semiconductor device is provided, the method including: select a plurality of integrated circuit semiconductor device component layouts of an entity of integrated circuit semiconductor device component layouts based on a shared set of parameters; perform at least one compatibility verification process for the selected plurality of integrated circuit semiconductor device component layouts with regard to an environment of the integrated circuit semiconductor device component at a predetermined position in an integrated circuit semiconductor device; and output a compatibility verification information indicating a result of the at least one compatibility verification process for the plurality of integrated circuit semiconductor device component layouts.
Inventor(s): Naveen K. MELLEMPUDI of Bangalore (IN) for intel corporation, DHEEVATSA MUDIGERE of Bangalore (IN) for intel corporation, DIPANKAR DAS of Pune (IN) for intel corporation, SRINIVAS SRIDHARAN of Bangalore (IN) for intel corporation
IPC Code(s): G06T1/20, G06F5/01, G06F7/501, G06F7/523, G06F7/544, G06F17/15, G06F17/16, G06N3/044, G06N3/045, G06N3/063, G06N3/084
CPC Code(s): G06T1/20
Abstract: one embodiment provides for a graphics processing unit to perform computations associated with a neural network, the graphics processing unit comprising a hardware processing unit having a dynamic precision fixed-point unit that is configurable to convert elements of a floating-point tensor to convert the floating-point tensor into a fixed-point tensor.
Inventor(s): Jiaxiang Jiang of Santa Clara CA (US) for intel corporation, Athmanarayanan Lakshmi Narayanan of San Bruno CA (US) for intel corporation, Nilesh Ahuja of Cupertino CA (US) for intel corporation, Ibrahima Jacques Ndiour of Chandler AZ (US) for intel corporation, Ergin Utku Genc of Portland OR (US) for intel corporation, Mahesh Subedar of Portland OR (US) for intel corporation, Omesh Tickoo of Portland OR (US) for intel corporation
IPC Code(s): G06T7/00
CPC Code(s): G06T7/0012
Abstract: systems, apparatus, articles of manufacture, and methods to detect anomalies in three-dimensional (3d) images are disclosed. example apparatus disclosed herein generate a first two-dimensional (2d) anomaly map corresponding to a first 2d image slice of a 3d image, the first 2d image slice corresponding to a first axis of the 3d image. disclosed example apparatus also generate a second 2d anomaly map corresponding to a second 2d image slice of the 3d image, the second 2d image slice corresponding to a second axis of the 3d image. disclosed example apparatus further generate a 3d anomaly volume based on the first 2d anomaly map and the second 2d anomaly detection, the 3d anomaly volume corresponding to the 3d image.
Inventor(s): Przemyslaw Maziewski of Gdansk (PL) for intel corporation, Lukasz Pindor of Pruszcz Gdanski (PL) for intel corporation, Sebastian Rosenkiewicz of Gdansk (PL) for intel corporation, Adam Kupryjanow of Gdansk (PL) for intel corporation
IPC Code(s): G10L21/0232, G10L25/30, H04R3/00
CPC Code(s): G10L21/0232
Abstract: a system, article, device, apparatus, and method for a multi-microphone audio signal unifier comprises receiving, by processor circuitry, an initial audio signal from one of multiple microphones arranged to provide the initial audio signal. this also includes modifying the initial audio signal comprising using at least one neural network (nn) to generate a unified audio signal that is more generic to a type of microphone than the initial audio signal.
Inventor(s): Sridhar GOVINDARAJU of Hillsboro OR (US) for intel corporation, Matthew J. PRINCE of Portland OR (US) for intel corporation
IPC Code(s): H01L21/8234, G06F30/39, H01L21/3105, H01L21/321, H01L21/768, H01L21/8238, H01L21/84, H01L23/00, H01L23/498, H01L23/532, H01L23/535, H01L27/02, H01L27/088, H01L27/092, H01L27/12, H01L29/06, H01L29/423, H01L29/66, H01L29/78
CPC Code(s): H01L21/823437
Abstract: embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. in one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. other embodiments may be described and/or claimed.
20240413031. ON DIE FLEXURE CONTROL DEVICE AND METHOD_simplified_abstract_(intel corporation)
Inventor(s): Chandru Periasamy of Portland OR (US) for intel corporation, Jagat Shakya of Hillsboro OR (US) for intel corporation, Joshua Jeremy Cardiel Rivera of Beaverton OR (US) for intel corporation, Jaime A. Sanchez of Beaverton OR (US) for intel corporation, Devesh Srivastava of Portland OR (US) for intel corporation, Feras Eid of Chandler AZ (US) for intel corporation, Matthew Zeman of Portland OR (US) for intel corporation, Xavier F. Brun of Chandler AZ (US) for intel corporation, Nabankur Deb of Beaverton OR (US) for intel corporation
IPC Code(s): H01L23/31, H01L21/56, H01L23/367, H01L23/373
CPC Code(s): H01L23/3135
Abstract: an electronic device and associated methods are disclosed. electronic devices are shown that include a semiconductor die and a patterned layer connected to a backside of the die. electronic devices are shown that include a pattern of elements across a patterned layer that varies across the backside of a die. electronic devices are further shown that include a compliant filler within elements in a patterned layer.
Inventor(s): Min Pei of Camas WA (US) for intel corporation, Ralph V. Miele of Hillsboro OR (US) for intel corporation, Lejie Liu of Portland OR (US) for intel corporation, Phil Geng of Washougal WA (US) for intel corporation, Caleb Million Tessema of Portland OR (US) for intel corporation
IPC Code(s): H01L23/467, H01L23/367, H01L23/40
CPC Code(s): H01L23/467
Abstract: integrated circuit packages with fluid spacers to improve pin load distribution are disclosed. an example apparatus includes an integrated circuit (ic) package, a circuit board, a socket to couple the ic package and the circuit board, a backplate coupled to the circuit board, a loading assembly to provide a stack load to the ic package, and a fluid liner positioned between the circuit board and the backplate.
20240413066. EMBEDDED SEMICONDUCTOR DEVICE_simplified_abstract_(intel corporation)
Inventor(s): Ranjul BALAKRISHNAN of Bangalore (IN) for intel corporation, Sandesh GEEJAGAARU KRISHNAMURTH of Bangalore (IN) for intel corporation, Parnasree MAITI of Bangalore (IN) for intel corporation
IPC Code(s): H01L23/498, H01L21/48, H01L23/00, H01L23/552
CPC Code(s): H01L23/49822
Abstract: according to various examples, a device is described. the device may include a package substrate. the device may also include a dielectric underfill layer disposed above the package substrate, wherein the package substrate comprises an embedded microstrip layer embedded in the dielectric underfill layer. the device may also include a semiconductor device embedded in the dielectric underfill layer and electrically coupled to the embedded microstrip of the package substrate. the device may also include an electromagnetic interference absorber above a top surface of the semiconductor device, wherein the semiconductor device is electrically coupled to the embedded microstrip layer of the package substrate.
20240413089. IMPROVING SIZE AND EFFICIENCY OF DIES_simplified_abstract_(intel corporation)
Inventor(s): Mathew J. MANUSHAROW of Phoenix AZ (US) for intel corporation, Jonathan ROSENFELD of Portland OR (US) for intel corporation
IPC Code(s): H01L23/538, H01L21/48, H01L23/00, H01L23/498, H01L23/64, H01L25/00, H01L25/065
CPC Code(s): H01L23/5383
Abstract: an integrated circuit package is disclosed. the integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (emib) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.
Inventor(s): Ayan Kar of Portland OR (US) for intel corporation, Kalyan C. Kolluru of Portland OR (US) for intel corporation
IPC Code(s): H01L27/02
CPC Code(s): H01L27/0262
Abstract: a two-terminal ic device may be used for esd protection. the ic device may include a deep n-well may be between a p-type substrate and a group of wells that includes a first p-well, a second p-well, and a n-well. there may be another well between the second p-well and the n-well. a p-type semiconductor structure may be formed in the p-well. two n-type semiconductor structures may be formed in the second p-well and the n-well, respectively. a contact of the p-type semiconductor structure may be electrically coupled to a contact of the n-type semiconductor structure in the second p-well. the two contacts may constitute the first terminal of the ic device. the contact of the n-type semiconductor structure in the n-well may constitute the second terminal of the ic device. the first p-well may have a greater dimension but lower dopant concentration than the second p-well or the n-well.
Inventor(s): Denzil Frost of Rio Rancho ID (US) for intel corporation
IPC Code(s): H01G4/30
CPC Code(s): H01L28/91
Abstract: disclosed herein are ic devices with three-dimensional metal-insulator-metal capacitor structures. an example ic device implementing such capacitor structures includes studs of a first insulator material, an insulator material surrounding and in contact with upper-most portions of sidewalls of the studs, a first electrically conductive material surrounding bottom-most portions of the sidewalls of the studs, and a second electrically conductive material surrounding middle portions of the sidewalls of the studs, wherein the insulator material further surrounds the second electrically conductive material over the middle portions of the sidewalls of the studs. the ic device further includes a third electrically conductive material surrounding the insulator material surrounding the middle portions and the upper-most portions of the studs.
Inventor(s): Patrick MORROW of Portland OR (US) for intel corporation, Kimin JUN of Portland OR (US) for intel corporation, Il-Seok SON of Portland OR (US) for intel corporation, Donald W. NELSON of Beaverton OR (US) for intel corporation
IPC Code(s): H01L29/78, H01L23/00, H01L23/14, H01L23/15, H01L23/31, H01L23/498, H01L29/417
CPC Code(s): H01L29/78
Abstract: an apparatus including a circuit structure including a first side including a device layer including a plurality of devices and an opposite second side; an electrically conductive contact coupled to one of the plurality of devices on the first side; and an electrically conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. a method including forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming an electrically conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact.
20240413550. FULLY SYMMETRIC SOCKET PIN ARRANGEMENT_simplified_abstract_(intel corporation)
Inventor(s): Chenghai Yan of Shanghai (CN) for intel corporation, Wenzhi Wang of Shanghai (CN) for intel corporation, Qihang Shang of Shanghai (CN) for intel corporation, Tao Xu of Shanghai (CN) for intel corporation, Weijiao Jiang of Shanghai (CN) for intel corporation, Xinjun Zhang of Shanghai (CN) for intel corporation, Lei Wang of Shanghai (CN) for intel corporation, Xiaorui Xu of Shanghai (CN) for intel corporation
IPC Code(s): H01R12/70, H01R13/6461
CPC Code(s): H01R12/7076
Abstract: an apparatus and method for reducing differential cross-talk in a cpu pin arrangement of a server motherboard are described. the cpu pin arrangement has pin patterns that are arranged in a square, separated from each other, and are mirrored around an axis between the pin patterns. each pin pattern has pins that each include a main body with a lateral asymmetric cross-section, a first connector extending from one end of the main body and coupled to the motherboard through solder, and a second connector extending from an opposing end of the main body and coupled to the cpu through a pressure contact.
Inventor(s): Richard S. PERRY of Portland OR (US) for intel corporation, Robert SCHUM of Beaverton OR (US) for intel corporation
IPC Code(s): H01R12/72, G06F1/16, G06F1/18, H01R12/52, H01R12/70, H01R12/73
CPC Code(s): H01R12/727
Abstract: a board-to-board connector includes electrical leads to bridge from one board to another board, to interconnect pads on one surface of the boards. the boards can interconnect while one board is vertically offset from the other board with a top mount connector. the connector includes a lead frame having the electrical leads and the connector includes an alignment frame to hold the lead frame. the lead frame includes leads that have contact arms that are vertically offset from each other. the connector includes a conductive case to secure over the alignment frame. the connector includes screw holes to allow screws to secure the connector in place against the boards and ensure electrical connection between the pads on the two boards through the electrical leads of the connector. the alignment frame includes posts to mate with alignment holes in the boards.
Inventor(s): Yizhi Yao of Chandler AZ (US) for intel corporation
IPC Code(s): H04L41/16, H04L41/12
CPC Code(s): H04L41/16
Abstract: this disclosure describes systems, methods, and devices for deploying machine learning (ml) models for wireless communications. a management service (mns) producer apparatus a may include processing circuitry coupled to storage for storing information associated with deploying machine learning (ml) models, the processing circuitry configured to: receive an ml model loading request, or identify an ml model loading policy, defining an ml model and a target inference function to which the ml model is to be loaded; instantiate an ml model loading process to load the ml model to the target inference function, the ml model loading processing comprising a progress status attribute indicative of a progress of loading the ml model to the target inference function; and create a managed object instance (moi) of the ml model under an moi of the target inference function based on completion of the loading of the ml model to the target inference function.
20240414171. ADDRESS VALIDATION FOR CONNECTION ESTABLISHMENT_simplified_abstract_(intel corporation)
Inventor(s): Bo CUI of Shanghai (CN) for intel corporation, Zhan XUE of Shanghai (CN) for intel corporation, Tingkai CHEN of Shanghai (CN) for intel corporation
IPC Code(s): H04L9/40, H04L67/141
CPC Code(s): H04L63/12
Abstract: examples described herein relate to an interface and circuitry. the circuitry can perform offloaded performance of a cryptographic handshake with a client in connection with initiation of a quick user datagram protocol internet connections (quic) connection with the client. in some examples, the cryptographic handshake comprises process a first client hello datagram from the client, the first client hello datagram is consistent with quic, and the offloaded performance of the cryptographic handshake with the client is offloaded from a processor to the circuitry.
Inventor(s): Alexey Khoryaev of Nizhny Novgorod (RU) for intel corporation, Artyom Lomayev of Nizhny Novgorod (RU) for intel corporation, Andrey Chervyakov of Maynooth (IE) for intel corporation, Sergey Sosnin of Zavolzhei (RU) for intel corporation
IPC Code(s): H04W64/00, H04L5/00, H04W24/10, H04W84/04
CPC Code(s): H04W64/00
Abstract: a non-transitory computer-readable storage medium stores instructions for execution by one or more processors of a ue. the instructions configure the ue for low latency nr positioning in a 5g nr network and cause the ue to perform operations comprising decoding configuration signaling received from a base station. the configuration signaling includes measurement gap information and scheduling information for a ue measurement report. a downlink (dl) positioning reference signal (prs) received from the base station is decoded. positioning measurements are performed using the dl prs. the positioning measurements are performed based on a measurement gap corresponding to the measurement gap information. the ue measurement report is encoded for a ul transmission to the base station based on the scheduling information. the ue measurement report includes the positioning measurements.
Intel Corporation patent applications on December 12th, 2024
- Intel Corporation
- F04D29/66
- F04D17/16
- F04D25/08
- F04D29/28
- G06F1/20
- CPC F04D29/666
- Intel corporation
- G01S13/76
- H04W64/00
- CPC G01S13/765
- G05D1/00
- B60W60/00
- G01C21/34
- G05D1/617
- CPC G05D1/0214
- G06F1/10
- G06F1/08
- G06F1/3206
- G06F16/9035
- CPC G06F1/10
- G06F3/01
- G06T13/80
- G06V10/143
- G06V40/19
- G10L15/02
- G10L15/22
- G10L15/30
- G10L21/003
- CPC G06F3/013
- G06F15/78
- G06F7/544
- G06F7/575
- G06F7/58
- G06F9/30
- G06F9/38
- G06F9/50
- G06F12/02
- G06F12/06
- G06F12/0802
- G06F12/0804
- G06F12/0811
- G06F12/0862
- G06F12/0866
- G06F12/0871
- G06F12/0875
- G06F12/0882
- G06F12/0888
- G06F12/0891
- G06F12/0893
- G06F12/0895
- G06F12/0897
- G06F12/1009
- G06F12/128
- G06F15/80
- G06F17/16
- G06F17/18
- G06N3/08
- G06T1/20
- G06T1/60
- G06T15/06
- H03M7/46
- CPC G06F15/7839
- G06F30/398
- G06F30/31
- G06F30/392
- CPC G06F30/398
- G06F5/01
- G06F7/501
- G06F7/523
- G06F17/15
- G06N3/044
- G06N3/045
- G06N3/063
- G06N3/084
- CPC G06T1/20
- G06T7/00
- CPC G06T7/0012
- G10L21/0232
- G10L25/30
- H04R3/00
- CPC G10L21/0232
- H01L21/8234
- G06F30/39
- H01L21/3105
- H01L21/321
- H01L21/768
- H01L21/8238
- H01L21/84
- H01L23/00
- H01L23/498
- H01L23/532
- H01L23/535
- H01L27/02
- H01L27/088
- H01L27/092
- H01L27/12
- H01L29/06
- H01L29/423
- H01L29/66
- H01L29/78
- CPC H01L21/823437
- H01L23/31
- H01L21/56
- H01L23/367
- H01L23/373
- CPC H01L23/3135
- H01L23/467
- H01L23/40
- CPC H01L23/467
- H01L21/48
- H01L23/552
- CPC H01L23/49822
- H01L23/538
- H01L23/64
- H01L25/00
- H01L25/065
- CPC H01L23/5383
- CPC H01L27/0262
- H01G4/30
- CPC H01L28/91
- H01L23/14
- H01L23/15
- H01L29/417
- CPC H01L29/78
- H01R12/70
- H01R13/6461
- CPC H01R12/7076
- H01R12/72
- G06F1/16
- G06F1/18
- H01R12/52
- H01R12/73
- CPC H01R12/727
- H04L41/16
- H04L41/12
- CPC H04L41/16
- H04L9/40
- H04L67/141
- CPC H04L63/12
- H04L5/00
- H04W24/10
- H04W84/04
- CPC H04W64/00