Intel Corporation patent applications on April 10th, 2025
Patent Applications by Intel Corporation on April 10th, 2025
Intel Corporation: 38 patent applications
Intel Corporation has applied for patents in the areas of G06F9/30 (8), G06F9/38 (5), G06T1/20 (4), G06F17/16 (3), G06F12/0875 (3) G06T1/20 (3), G06F9/30025 (2), G06F9/30036 (2), G06F15/8046 (2), H04W12/0433 (1)
With keywords such as: memory, data, device, matrix, circuitry, network, embodiments, apparatus, source, and based in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): Abhishek A. Sharma of Portland OR US for intel corporation, Wilfred Gomes of Portland OR US for intel corporation
IPC Code(s): G02B6/132, G02B6/12, G02B6/136
CPC Code(s): G02B6/132
Abstract: described herein are stacked photonic integrated circuit (pic) assemblies that include multiple layers of waveguides. the waveguides are formed of substantially monocrystalline materials, which cannot be repeatedly deposited. layers of monocrystalline material are fabricated and repeatedly transferred onto the pic structure using a layer transfer process, which involves bonding a monocrystalline material using a non-monocrystalline bonding material. layers of isolation materials are also deposited or layer transferred onto the pic assembly.
20250117060. PROCESSOR POWER MANAGEMENT_simplified_abstract_(intel corporation)
Inventor(s): Altug Koker of El Dorado Hills CA US for intel corporation, Abhishek R. Appu of El Dorado Hills CA US for intel corporation, Kiran C. Veernapu of Bangalore IN for intel corporation, Joydeep Ray of Folsom CA US for intel corporation, Balaji Vembu of Folsom CA US for intel corporation, Prasoonkumar Surti of Folsom CA US for intel corporation, Kamal Sinha of Folsom CA US for intel corporation, Eric J. Hoekstra of Folsom CA US for intel corporation, Wenyin Fu of Folsom CA US for intel corporation, Nikos Kaburlasos of Folsom CA US for intel corporation, Bhushan M. Borole of Rancho Cordova CA US for intel corporation, Travis T. Schluessler of Berthoud CO US for intel corporation, Ankur N. Shah of Folsom CA US for intel corporation, Jonathan Kennedy of Bristol GB for intel corporation
IPC Code(s): G06F1/26, G06F12/0875
CPC Code(s): G06F1/3209
Abstract: methods and apparatus relating to techniques for avoiding cache lookup for cold cache. in an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. other embodiments are also disclosed and claimed.
Inventor(s): Kristoffer Fleming of Chandler AZ US for intel corporation, Melanie Daniels of Folsom CA US for intel corporation, Paul Diefenbaugh of Portland OR US for intel corporation, Aleksander Magi of Portland OR US for intel corporation, Lawrence Falkenstein of Hillsboro OR US for intel corporation, Raoul Rivas Toledano of Beaverton OR US for intel corporation, Vishal Sinha of Portland OR US for intel corporation, Deepak Samuel Kirubakaran of Hillsboro OR US for intel corporation, Venkateshan Udhayan of Portland OR US for intel corporation, Marko Bartscherer of Chula Vista CA US for intel corporation, Kathy Bui of Hillsboro OR US for intel corporation
IPC Code(s): G06F1/3231, G06F1/3234, G06N20/00, G06V40/10, G10L15/08, G10L15/18, G10L15/22, G10L15/30, H04N23/65, H04W52/02
CPC Code(s): G06F1/3231
Abstract: methods and apparatus to improve user experience on computing devices are disclosed. an example computing device includes a microphone to capture audio corresponding to spoken words. the example computing device further includes a speech analyzer to: detect a keyword prompt from among the spoken words, the keyword prompt to precede a query statement of a user of the computing device; and identify topics associated with a subset of the spoken words, the subset of the spoken words captured by the microphone before the keyword prompt. the example computing device also includes a communications interface to, in response to detection of the keyword prompt, transmit information indicative of the query statement and ones of the identified topics to a remote server.
Inventor(s): Alexander F. HEINECKE of San Jose CA US for intel corporation, Robert VALENTINE of Kiryat Tivon IL for intel corporation, Mark J. CHARNEY of Lexington MA US for intel corporation, Raanan SADE of Portland OR US for intel corporation, Menachem ADELMAN of Modi'in IL for intel corporation, Zeev SPERBER of Zichron Yackov IL for intel corporation, Amit GRADSTEIN of Binyamina IL for intel corporation, Simon RUBANOVICH of Haifa IL for intel corporation
IPC Code(s): G06F9/30, G06F9/38
CPC Code(s): G06F9/30025
Abstract: disclosed embodiments relate to systems and methods for performing instructions to convert to 16-bit floating-point format. in one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode and locations of a first source vector comprising n single-precision elements, and a destination vector comprising at least n 16-bit floating-point elements, the opcode to indicate execution circuitry is to convert each of the elements of the specified source vector to 16-bit floating-point, the conversion to include truncation and rounding, as necessary, and to store each converted element into a corresponding location of the specified destination vector, decode circuitry to decode the fetched instruction, and execution circuitry to respond to the decoded instruction as specified by the opcode.
20250117218. INSTRUCTIONS TO CONVERT FROM FP16 TO BF8_simplified_abstract_(intel corporation)
Inventor(s): Alexander Heinecke of San Jose CA US for intel corporation, Naveen Mellempudi of Bangalore IN for intel corporation, Robert Valentine of Kiryat Tivon IL for intel corporation, Mark Charney of Lexington MA US for intel corporation, Christopher Hughes of Santa Clara CA US for intel corporation, Evangelos Georganas of San Mateo CA US for intel corporation, Zeev Sperber of Zichron Yackov IL for intel corporation, Amit Gradstein of Binyamina IL for intel corporation, Simon Rubanovich of Haifa IL for intel corporation
IPC Code(s): G06F9/30, G06F9/38
CPC Code(s): G06F9/30025
Abstract: techniques for converting fp16 to bf8 using bias are described. an exemplary embodiment utilizes decoder circuitry to decode a single instruction, the single instruction to include one or more fields to identify a first source operand, one or more fields to identify a second source operand, one or more fields to identify a source/destination operand, and one or more fields for an opcode, wherein the opcode is to indicate that execution circuitry is to convert packed half-precision data from the identified first and second sources to packed bfloat8 data using bias terms from the identified source/destination operand and store the packed bfloat8 data into corresponding data element positions of the identified source/destination operand; and execution circuitry to execute the decoded instruction according to the opcode to convert packed half-precision data from the identified first and second sources to packed bfloat8 data using bias terms from the identified source/destination operand and store the packed bfloat8 data into corresponding data element positions of the identified source/destination operand.
Inventor(s): Robert VALENTINE of Kiryat Tivon IL for intel corporation, Dan BAUM of Haifa IL for intel corporation, Zeev SPERBER of Zichron Yackov IL for intel corporation, Jesus CORBAL of King City OR US for intel corporation, Elmoustapha OULD-AHMED-VALL of Gilbert AZ US for intel corporation, Bret L. TOLL of Hillsboro OR US for intel corporation, Mark J. CHARNEY of Lexington MA US for intel corporation, Barukh ZIV of Haifa IL for intel corporation, Alexander HEINECKE of San Jose CA US for intel corporation, Milind GIRKAR of Sunnyvale CA US for intel corporation, Menachem ADELMAN of Modi'in IL for intel corporation, Simon RUBANOVICH of Haifa IL for intel corporation
IPC Code(s): G06F9/30, G06F7/78
CPC Code(s): G06F9/30036
Abstract: embodiments detailed herein relate to matrix operations. in particular, support for a matrix transpose instruction is detailed. in some embodiments, decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry to execute the decoded instruction to transpose each row of elements of the identified source matrix operand into a corresponding column of the identified destination matrix operand are detailed.
Inventor(s): Robert VALENTINE of Kiryat Tivon IL for intel corporation, Zeev SPERBER of Zichron Yackov IL for intel corporation, Mark J. CHARNEY of Lexington MA US for intel corporation, Bret L. TOLL of Hillsboro OR US for intel corporation, Rinat RAPPOPORT of Haifa IL for intel corporation, Stanislav SHWARTSMAN of Haifa IL for intel corporation, Dan BAUM of Haifa IL for intel corporation, Igor YANOVER of Yokneam Illit IL for intel corporation, Elmoustapha OULD-AHMED-VALL of Chandler AZ US for intel corporation, Menachem ADELMAN of Haifa IL for intel corporation, Jesus CORBAL of King City OR US for intel corporation, Yuri GEBIL of Nahariya IL for intel corporation, Simon RUBANOVICH of Haifa IL for intel corporation
IPC Code(s): G06F9/30
CPC Code(s): G06F9/30036
Abstract: embodiments detailed herein relate to matrix operations. in particular, matrix (tile) multiply accumulate and negated matrix (tile) multiply accumulate are discussed. for example, in some embodiments decode circuitry to decode an instruction having fields for an opcode, an identifier for a first source matrix operand, an identifier of a second source matrix operand, and an identifier for a source/destination matrix operand; and execution circuitry to execute the decoded instruction to multiply the identified first source matrix operand by the identified second source matrix operand, add a result of the multiplication to the identified source/destination matrix operand, and store a result of the addition in the identified source/destination matrix operand and zero unconfigured columns of identified source/destination matrix operand are detailed.
Inventor(s): Utkarsh Y. KAKAIYA of El Dorado Hills CA US for intel corporation, Rajesh M. SANKARAN of Portland OR US for intel corporation, Sanjay KUMAR of Hillsboro OR US for intel corporation, Kun TIAN of Shanghai CN for intel corporation, Philip LANTZ of Cornelius OR US for intel corporation
IPC Code(s): G06F9/54, G06F9/455, G06F9/48, G06F15/17
CPC Code(s): G06F9/5077
Abstract: techniques for scalable virtualization of an input/output (i/o) device are described. an electronic device composes a virtual device comprising one or more assignable interface (ai) instances of a plurality of ai instances of a hosting function exposed by the i/o device. the electronic device emulates device resources of the i/o device via the virtual device. the electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more ai instances of the i/o device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. for a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.
Inventor(s): Raghunandan MAKARAM of Northborough MA US for intel corporation, Kirk S. YAP of Westborough MA US for intel corporation
IPC Code(s): G06F11/10, H04L9/32, H04L69/22
CPC Code(s): G06F11/1004
Abstract: in one embodiment, an apparatus includes: an integrity circuit to receive data and generate a protection code based at least in part on the data; a cryptographic circuit coupled to the integrity circuit to encrypt the data into encrypted data and encrypt the protection code into an encrypted protection code; a message authentication code (mac) circuit coupled to the cryptographic circuit to compute a mac comprising a tag using header information, the encrypted data, and the encrypted protection code; and an output circuit to send the header information, the encrypted data, and the tag to a receiver via a link. other embodiments are described and claimed.
Inventor(s): Sunku Ranganath of Beaverton OR for intel corporation, John Browne of Limerick IE for intel corporation, Hassnaa Moustafa of San Jose CA US for intel corporation, Mandar Chincholkar of Portland OR US for intel corporation, Amar Srivastava of Bangalore IN for intel corporation
IPC Code(s): G06F12/02
CPC Code(s): G06F12/023
Abstract: memory management for wireless networks is described. a method, includes accessing an operational parameter for a network slice of a wireless network, determining a first memory region of a plurality of memory regions in the memory pool based on the operational parameter, and encoding configuration information to allocate the first memory region to the network slice. other embodiments are described and claimed.
Inventor(s): Jayesh Gaur of Bangalore IN for intel corporation, Adarsh Chauhan of Bangalore IN for intel corporation, Vinodh Gopal of Westborough MA US for intel corporation, Vedvyas Shanbhogue of Austin TX US for intel corporation, Sreenivas Subramoney of Bangalore IN for intel corporation, Wajdi Feghali of Boston MA US for intel corporation
IPC Code(s): G06F12/0893, G06F12/0875
CPC Code(s): G06F12/0811
Abstract: methods and apparatus relating to an instruction and/or micro-architecture support for decompression on core are described. in an embodiment, decode circuitry decodes a decompression instruction into a first micro operation and a second micro operation. the first micro operation causes one or more load operations to fetch data into one or more cachelines of a cache of a processor core. decompression engine (de) circuitry decompresses the fetched data from the one or more cachelines of the cache of the processor core in response to the second micro operation. other embodiments are also disclosed and claimed.
Inventor(s): Saravanan SETHURAMAN of Portland OR US for intel corporation, George VERGIS of Portland OR US for intel corporation
IPC Code(s): G06F13/16
CPC Code(s): G06F13/1668
Abstract: a system includes a memory die stack that provides sensing information via proxy. the memory die stack includes at least a first memory die with a sensor that generates sensing data for the first memory die and a second memory die with a sensor that generates sensing data for the second memory die. the proxy is a logic device that aggregates and sends the sensing data for both memory dies over a management communication bus.
20250117356. MULTI-TILE MEMORY MANAGEMENT_simplified_abstract_(intel corporation)
Inventor(s): Abhishek R. Appu of El Dorado Hills CA US for intel corporation, Altug Koker of El Dorado Hills CA US for intel corporation, Aravindh Anantaraman of Folsom CA US for intel corporation, Elmoustapha Ould-Ahmed-Vall of Chandler AZ US for intel corporation, Valentin Andrei of San Jose CA US for intel corporation, Nicolas Galoppo Von Borries of Portland OR US for intel corporation, Varghese George of Folsom CA US for intel corporation, Mike Macpherson of Portland OR US for intel corporation, Subramaniam Maiyuran of Gold River CA US for intel corporation, Joydeep Ray of Folsom CA US for intel corporation, Lakshminarayanan Striramassarma of Folsom CA US for intel corporation, Scott Janus of Loomis CA US for intel corporation, Brent Insko of Portland OR US for intel corporation, Vasanth Ranganathan of El Dorado Hills CA US for intel corporation, Kamal Sinha of Rancho Cordova CA US for intel corporation, Arthur Hunter of Cameron Park CA US for intel corporation, Prasoonkumar Surti of Folsom CA US for intel corporation, David Puffer of Tempe AZ US for intel corporation, James Valerio of North Plains OR US for intel corporation, Ankur N. Shah of Folsom CA US for intel corporation
IPC Code(s): G06F15/78, G06F7/544, G06F7/575, G06F7/58, G06F9/30, G06F9/38, G06F9/50, G06F12/02, G06F12/06, G06F12/0802, G06F12/0804, G06F12/0811, G06F12/0862, G06F12/0866, G06F12/0871, G06F12/0875, G06F12/0882, G06F12/0891, G06F12/0893, G06F12/0895, G06F12/0897, G06F12/1009, G06F12/128, G06F15/80, G06F17/16, G06F17/18, G06N3/08, G06T1/20, G06T1/60, G06T15/06, H03M7/46
CPC Code(s): G06F15/7839
Abstract: methods and apparatus relating to techniques for multi-tile memory management. in an example, a graphics processor includes an interposer, a first chiplet coupled with the interposer, the first chiplet including a graphics processing resource and an interconnect network coupled with the graphics processing resource, cache circuitry coupled with the graphics processing resource via the interconnect network, and a second chiplet coupled with the first chiplet via the interposer, the second chiplet including a memory-side cache and a memory controller coupled with the memory-side cache. the memory controller is configured to enable access to a high-bandwidth memory (hbm) device, the memory-side cache is configured to cache data associated with a memory access performed via the memory controller, and the cache circuitry is logically positioned between the graphics processing resource and a chiplet interface.
20250117359. DUAL PIPELINE PARALLEL SYSTOLIC ARRAY_simplified_abstract_(intel corporation)
Inventor(s): Jorge Parra of El Dorado Hills CA US for intel corporation, Jiasheng Chen of El Dorado Hills CA US for intel corporation, Supratim Pal of Folsom CA US for intel corporation, Fangwen Fu of Folsom CA US for intel corporation, Sabareesh Ganapathy of Bangalore IN for intel corporation, Chandra Gurram of Folsom CA US for intel corporation, Chunhui Mei of San Diego CA US for intel corporation, Yue Qi of San Diego CA US for intel corporation
IPC Code(s): G06F9/38, G06F9/30
CPC Code(s): G06F15/8046
Abstract: a processing apparatus described herein includes a general-purpose parallel processing engine comprising a systolic array having multiple pipelines, each of the multiple pipelines including multiple pipeline stages, wherein the multiple pipelines include a first pipeline, a second pipeline, and a common input shared between the first pipeline and the second pipeline.
Inventor(s): Jorge Parra of El Dorado Hills CA US for intel corporation, Wei-yu Chen of San Jose CA US for intel corporation, Kaiyu Chen of San Jose CA US for intel corporation, Varghese George of Folsom CA US for intel corporation, Junjie Gu of Santa Clara CA US for intel corporation, Chandra Gurram of Folsom CA US for intel corporation, Guei-Yuan Lueh of San Jose CA US for intel corporation, Stephen Junkins of Bend OR US for intel corporation, Subramaniam Maiyuran of Gold River CA US for intel corporation, Supratim Pal of Folsom CA US for intel corporation
IPC Code(s): G06F15/80, G06F9/30
CPC Code(s): G06F15/8046
Abstract: a processing apparatus includes a processing resource including a general-purpose parallel processing engine and a matrix accelerator. the matrix accelerator includes first circuitry to receive a command to perform operations associated with an instruction, second circuitry to configure the matrix accelerator according to a physical depth of a systolic array within the matrix accelerator and a logical depth associated with the instruction, third circuitry to read operands for the instruction from a register file associated with the systolic array, fourth circuitry to perform operations for the instruction via one or more passes through one or more physical pipeline stages of the systolic array based on a configuration performed by the second circuitry, and fifth circuitry to write output of the operations to the register file associated with the systolic array.
Inventor(s): Prashant Dewan of Portland OR US for intel corporation, Baiju Patel of Portland OR US for intel corporation
IPC Code(s): G06F21/79, G06F12/14, G06F13/28, G06F21/60, G06F21/62, G06F21/85
CPC Code(s): G06F21/602
Abstract: the disclosed embodiments are generally directed to inline encryption of data at line speed at a chip interposed between two memory components. the inline encryption may be implemented at a system-on-chip (“soc” or “soc”). the memory components may comprise non-volatile memory express (nvme) and a dynamic random access memory (dram). an exemplary device includes an soc to communicate with a non-volatile memory nvme circuitry to provide direct memory access (dma) to an external memory component. the soc may include: a cryptographic controller circuitry; a cryptographic memory circuitry in communication with the cryptographic controller, the cryptographic memory circuitry configured to store instructions to encrypt or decrypt data transmitted through the soc; and an encryption engine in communication with the crypto controller circuitry, the encryption engine configured to encrypt or decrypt data according to instructions stored at the crypto memory circuitry. other embodiments are also disclosed and claimed.
Inventor(s): Anthony Daniel Rhodes of Portland OR US for intel corporation, Ramesh Radhakrishna Manuvinakurike of Hillsboro OR US for intel corporation, Sovan Biswas of Bonn DE for intel corporation, Giuseppe Raffa of Portland OR US for intel corporation, Lama Nachman of Santa Clara CA US for intel corporation
IPC Code(s): G06N3/0475
CPC Code(s): G06N3/0475
Abstract: predictive uncertainty of a generative machine learning model may be estimated. the generative machine learning model may be a large language model or large multi-modal model. a datum may be input into the generative machine learning model. the generative machine learning model may generate outputs from the datum. latent embeddings for the outputs may be extracted from the generative machine learning model. a covariance matrix with respect to the latent embeddings may be computed. the covariance matrix may be a two-dimensional matrix, such as a square matrix. the predictive uncertainty of the generative machine learning model may be estimated using the covariance matrix. for instance, the matrix entropy of the covariance matrix may be determined. the matrix entropy may be an approximated dimension of a latent semantic manifold spanned by the outputs of the generative machine learning model and may indicate the predictive uncertainty of the generative machine learning model.
Inventor(s): Anbang Yao of Beijing CN for intel corporation, Aojun Zhou of Beijing CN for intel corporation, Kuan Wang of Beijing CN for intel corporation, Hao Zhao of Beijing CN for intel corporation, Yurong Chen of Beijing CN for intel corporation
IPC Code(s): G06N3/063, G06F18/21, G06F18/214, G06N3/047, G06N3/084
CPC Code(s): G06N3/063
Abstract: methods, apparatus, systems and articles of manufacture for loss-error-aware quantization of a low-bit neural network are disclosed. an example apparatus includes a network weight partitioner to partition unquantized network weights of a first network model into a first group to be quantized and a second group to be retrained. the example apparatus includes a loss calculator to process network weights to calculate a first loss. the example apparatus includes a weight quantizer to quantize the first group of network weights to generate low-bit second network weights. in the example apparatus, the loss calculator is to determine a difference between the first loss and a second loss. the example apparatus includes a weight updater to update the second group of network weights based on the difference. the example apparatus includes a network model deployer to deploy a low-bit network model including the low-bit second network weights.
Inventor(s): Anjali Singhai Jain of Portland OR US for intel corporation, Tamar Bar-Kanarik of Ramat Hasharon IL for intel corporation, Marcos Carranza of Portland OR US for intel corporation, Karthik Kumar of Chandler AZ US for intel corporation, Cristian Florin Dumitrescu of Shannon IE for intel corporation, Keren Guy of San Jose CA US for intel corporation, Patrick Connor of Beaverton OR US for intel corporation
IPC Code(s): G06N5/04, G06N3/02
CPC Code(s): G06N5/04
Abstract: techniques described herein address the above challenges that arise when using host executed software to manage vector databases by providing a vector database accelerator and shard management offload logic that is implemented within hardware and by software executed on device processors and programmable data planes of a programmable network interface device. in one embodiment, a programmable network interface device includes infrastructure management circuitry configured to facilitate data access for a neural network inference engine having a distributed data model via dynamic management of a node associated with the neural network inference engine, the node including a database shard of a vector database.
20250117873. MACHINE LEARNING SPARSE COMPUTATION MECHANISM_simplified_abstract_(intel corporation)
Inventor(s): Eriko Nurvitadhi of Hillsboro OR US for intel corporation, Balaji Vembu of Folsom CA US for intel corporation, Tsung-Han Lin of Campbell CA US for intel corporation, Kamal Sinha of Rancho Cordova CA US for intel corporation, Rajkishore Barik of Santa Clara CA US for intel corporation, Nicolas C. Galoppo Von Borries of Portland OR US for intel corporation
IPC Code(s): G06T1/20, G06F9/38, G06F17/16
CPC Code(s): G06T1/20
Abstract: techniques to improve performance of matrix multiply operations are described in which a compute kernel can specify one or more element-wise operations to perform on output of the compute kernel before the output is transferred to higher levels of a processor memory hierarchy.
Inventor(s): Elmoustapha Ould-Ahmed-Vall of Chandler AZ US for intel corporation, Sara S. Baghsorkhi of San Jose CA US for intel corporation, Anbang Yao of Beijing CN for intel corporation, Kevin Nealis of San Jose CA US for intel corporation, Xiaoming Chen of Shanghai CN for intel corporation, Altug Koker of El Dorado Hills CA US for intel corporation, Abhishek R. Appu of El Dorado Hills CA US for intel corporation, John C. Weast of Portland OR US for intel corporation, Mike B. Macpherson of Portland OR US for intel corporation, Dukhwan Kim of San Jose CA US for intel corporation, Linda L. Hurd of Cool CA US for intel corporation, Ben J. Ashbaugh of Folsom CA US for intel corporation, Barath Lakshmanan of Chandler AZ US for intel corporation, Liwei Ma of Beijing CN for intel corporation, Joydeep Ray of Folsom CA US for intel corporation, Ping T. Tang of Edison NJ US for intel corporation, Michael S. Strickland of Sunnyvale CA US for intel corporation
IPC Code(s): G06F17/16, G06F7/544
CPC Code(s): G06T1/20
Abstract: one embodiment provides an apparatus comprising a memory stack including multiple memory dies and a parallel processor including a plurality of multiprocessors. each multiprocessor has a single instruction, multiple thread (simt) architecture, the parallel processor coupled to the memory stack via one or more memory interfaces. at least one multiprocessor comprises a multiply-accumulate circuit to perform multiply-accumulate operations on matrix data in a stage of a neural network implementation to produce a result matrix comprising a plurality of matrix data elements at a first precision, precision tracking logic to evaluate metrics associated with the matrix data elements and indicate if an optimization is to be performed for representing data at a second stage of the neural network implementation, and a numerical transform unit to dynamically perform a numerical transform operation on the matrix data elements based on the indication to produce transformed matrix data elements at a second precision.
20250117875. REDUCE POWER BY FRAME SKIPPING_simplified_abstract_(intel corporation)
Inventor(s): Balaji Vembu of Folsom CA US for intel corporation, Nikos Kaburlasos of Folsom CA US for intel corporation, Josh B. Mastronarde of Sacramento CA US for intel corporation
IPC Code(s): G06T1/20, G06F1/3203, G06F1/3231, G06F1/3234, G06T1/60
CPC Code(s): G06T1/20
Abstract: in an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive an input from one or more detectors proximate a display to present an output from a graphics pipeline, determine that a user is not interacting with the display, and in response to a determination that the user is not interacting with the display, to reduce a frame rendering rate of the graphics pipeline. other embodiments are also disclosed and claimed.
Inventor(s): John Wiegert of Aloha OR US for intel corporation, Joydeep Ray of Folsom CA US for intel corporation, Fabian Schnell of Scotts Valley CA US for intel corporation, Kelvin Thomas Gardiner of Rancho Cordova CA US for intel corporation
IPC Code(s): G06T1/20, G06F9/30, G06F11/34, G06T1/60
CPC Code(s): G06T15/005
Abstract: an apparatus to facilitate exception handling for debugging in a graphics environment is disclosed. the apparatus includes load store pipeline hardware circuitry to: in response to a page fault exception being enabled for a memory access request received from a thread of the plurality of threads, allocate a memory dependency token correlated to a scoreboard identifier (sbid) that is included with the memory access request; send, to memory fabric of the graphics processor, the memory access request comprising the memory dependency token; receive, from the memory fabric in response to the memory access request, a memory access response comprising the memory dependency token and indicating occurrence of a page fault error condition and fault details associated with the page fault error condition; and return the sbid associated with the memory access response and fault details of the page fault error condition to a debug register of the thread.
20250118641. PLANAR INTEGRATED CIRCUIT PACKAGE INTERCONNECTS_simplified_abstract_(intel corporation)
Inventor(s): Robert L. Sankman of Phoenix AZ US for intel corporation, Sanka Ganesan of Chandler AZ US for intel corporation
IPC Code(s): H01L23/00, H01L23/31, H05K1/18
CPC Code(s): H01L23/49811
Abstract: generally discussed herein are systems, methods, and apparatuses that include conductive pillars that are about co-planar. according to an example, a technique can include growing conductive pillars on respective exposed landing pads of a substrate, situating molding material around and on the grown conductive pillars, removing, simultaneously, a portion of the grown conductive pillars and the molding material to make the grown conductive pillars and the molding material about planar, and electrically coupling a die to the conductive pillars.
Inventor(s): Srinivas V. PIETAMBARAM of Chandler AZ US for intel corporation, Debendra MALLIK of Chandler AZ US for intel corporation, Kristof DARMAWIKARTA of Chandler AZ US for intel corporation, Ravindranath V. MAHAJAN of Chandler AZ US for intel corporation, Rahul N. MANEPALLI of Chandler AZ US for intel corporation
IPC Code(s): H01L23/498, H01L23/00, H01L23/538, H01L25/065
CPC Code(s): H01L23/49822
Abstract: an electronic package includes an interposer having an interposer substrate, a cavity that passes into but not through the interposer substrate, a through interposer via (tiv) within the interposer substrate, and an interposer pad electrically coupled to the tiv. the electronic package includes a nested component in the cavity, wherein the nested component includes a component pad coupled to a through-component via. a core via is beneath the nested component, the core via extending from the nested component through the interposer substrate. a die is coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect.
Inventor(s): Xavier Francois Brun of Hillsboro OR US for intel corporation, Sanka Ganesan of Chandler AZ US for intel corporation, Holly Sawyer of Aloha OR US for intel corporation, William J. Lambert of Chandler AZ US for intel corporation, Timothy A. Gosselin of Phoenix AZ US for intel corporation, Yuting Wang of Chandler AZ US for intel corporation
IPC Code(s): H01L25/11, H01L23/00, H01L23/538
CPC Code(s): H01L24/29
Abstract: microelectronic assemblies, related devices and methods, are disclosed herein. in some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (rdl) on the first layer, wherein the rdl is electrically coupled to the second surface of the first die by solder interconnects, and a second die in a second layer on the rdl, wherein the second die is electrically coupled to the rdl by non-solder interconnects.
Inventor(s): Kai XIAO of Portland OR US for intel corporation, Diego Mauricio CORTES HERNANDEZ of Beaverton OR US for intel corporation, Luz Karine SANDOVAL GRANADOS of Zapopan MX for intel corporation, Jingbo LI of Portland OR US for intel corporation, Raul ALCALA ARREOLA of Zapopan MX for intel corporation, Quresh BOHRA of San Jose CA US for intel corporation, Jose Manuel CANTOR GONZALEZ of Zapopan MX for intel corporation, Fabio RUIZ MOLINA of Zapopan MX for intel corporation, Carlos Guillermo TERRIQUEZ ARIAS of Zapopan MX for intel corporation, Adriana LOPEZ INIGUEZ of Zapopan MX for intel corporation
IPC Code(s): H01R13/6471, H01R12/70, H01R12/71, H01R12/75, H01R13/04
CPC Code(s): H01R13/6471
Abstract: examples include techniques to improve signal integrity performance for a 3-connector design. the techniques include mounting a socket connector to a first side of a hot swap backplane such that pins of the first socket connector mirror pins of a second socket connector mounted to a second side of the hot swap backplane. the mirrored pins associated with routing data signals. the socket connector having a housing configured to receive a first plug connector of a cable assembly that has a second plug connector coupled with a processor baseboard socket connector.
Inventor(s): Balvinder Pal Singh of Bhilai IN for intel corporation, Kobi Guetta of Netanya IL for intel corporation, Yoni Kahana of Kfar Hess IL for intel corporation, Amichay Israel of Haifa HA IL for intel corporation, Ehud Apsel of Sitria IL for intel corporation, Anubhav David of Gopalpur IN for intel corporation, Gila Kamhi of Zichron Yaakov HA IL for intel corporation
IPC Code(s): H04L41/0631, H04L41/069, H04L41/16, H04W24/02
CPC Code(s): H04L41/0631
Abstract: logic may monitor quality of communication of data to a wireless receiver device based on transport characteristics at a wireless source device. logic may evaluate the transport characteristics to identify indication(s) of a problem with the quality of the communication. logic may identify a root cause associated with the indication(s). logic may associate the root cause with one or more actions to mitigate the degradation of the quality. and logic may cause performance of an operation to mitigate the degradation of the quality based on the one or more actions. the logic to evaluate the transport characteristics may determine an upper limit for an achievable mean opinion score (mos) based on the transport characteristics; and, based on the upper limit for the achievable mos being less than a threshold mos, may identify the indication(s) associated with the upper limit for the achievable mos.
Inventor(s): Hossein FARROKHBAKHT of Toronto CA for intel corporation, Kartik LAKHOTIA of San Jose CA US for intel corporation, Gurpreet Singh KALSI of Portland OR US for intel corporation, Fabrizio PETRINI of Menlo Park CA US for intel corporation
IPC Code(s): H04L47/24, H04L47/12, H04L47/26
CPC Code(s): H04L47/24
Abstract: examples described herein relate to a switch or router. in some examples, the switch or router is to: based on receipt of a control packet associated with a first link, store the control packet into a first region of memory associated with the first link; based on receipt of a data packet associated with the first link, store the data packet into a second region of memory associated with the first link; based on the control packet and data packet to egress from a same output port, insert a strict subset of content of the control packet into the data packet to form a second data packet; and cause transmission of the second data packet to a device from the output port.
Inventor(s): Hossein FARROKHBAKHT of Toronto CA for intel corporation, Fabrizio PETRINI of Menlo Park CA US for intel corporation
IPC Code(s): H04L49/253, H04L49/112
CPC Code(s): H04L49/254
Abstract: examples described herein relate to switch circuitry that is to: based on receipt of a packet at the first input port and based on allocation of a first memory region in the memory to the first input port: based on capability of a first buffer for the first output port to store the packet, store the packet into the first buffer and egress the packet from the first buffer to the first output port and based on incapability of the first buffer to store the packet, store the packet into the first memory region and associate the packet with the first buffer prior to egress from the first output port.
Inventor(s): Po-Kai HUANG of San Ramon CA US for intel corporation, Ilan PEER of Modiin IL for intel corporation, Johannes BERG of Detmold DE for intel corporation, Ido OUZIELI of Tel Aviv IL for intel corporation, Elad OREN of Tel Aviv IL for intel corporation, Emily QI of Gig Harbor WA US for intel corporation
IPC Code(s): H04W12/041, H04W12/033, H04W12/0433
CPC Code(s): H04W12/0433
Abstract: this disclosure describes systems, methods, and devices related to using encrypted 802.11 association. a device may identify a beacon received from an access point (ap), the beacon including an indication of an authentication and key manager (akm); transmit, to the ap, an 802.11 authentication request including an indication of parameters associated with the akm; identify an 802.11 authentication response received from the ap based on the 802.11 authentication request, the 802.11 authentication response including a message integrity check (mic) using a key confirmation key (kck) and an indication that the parameters have been selected by the ap; transmit, to the ap, an 802.11 association request encrypted by a security key based on an authenticator address of the ap; and identify an 802.11 association response received from the ap based on the 802.11 association request, the 802.11 association response encrypted by the security key.
Inventor(s): Po-Kai Huang of San Jose CA US for intel corporation, Daniel F. Bravo of Portland OR US for intel corporation, Danny Alexander of Neve Efraim Monoson IL for intel corporation, Arik Klein of Givaat Shmuel IL for intel corporation, Danny Ben-Ari of Tsur Natan IL for intel corporation, Laurent Cariou of Milizac FR for intel corporation, Robert Stacey of Portland OR US for intel corporation
IPC Code(s): H04L5/00
CPC Code(s): H04W24/04
Abstract: this disclosure describes systems, methods, and devices related to high throughput (ht) control information. a device may determine a frame comprising ht control information. the device may determine to extend a size of the ht control information. the device may cause to generate a management or data frame for sending to a first station device of one or more station devices, the management or data frame comprising extended high throughput (ht) control information, define a new control identification (id) associated with the extended ht control information, and cause to send the management or data frame to the first station device.
Inventor(s): Gang Xiong of Portland OR US for intel corporation, Alexei Davydov of Santa Clara CA US for intel corporation, Bishwarup Mondal of San Ramon CA US for intel corporation, Dong Han of Santa Clara CA US for intel corporation
IPC Code(s): H04W72/1268, H04W76/38
CPC Code(s): H04W72/1268
Abstract: various embodiments herein provide techniques for uplink control information (uci) multiplexing in multi—transmission-reception point (trp) multi-panel operation. for example, the uci may be multiplexed on a physical uplink shared channel (pusch) and/or a physical uplink control channel (pucch). embodiments further include techniques for handling collision between pusch and pucch with different priorities. additionally, embodiments include techniques for timing control for multi-trp multi-panel operation. other embodiments may be described and claimed.
20250120036. RACKSIDE AUTOMATION FOR DATACENTER OPTIMIZATION_simplified_abstract_(intel corporation)
Inventor(s): Ralph Jensen of Tumwater WA US for intel corporation, Michael Crocker of Portland OR US for intel corporation, Carl Williams of Manitou Springs CO US for intel corporation
IPC Code(s): H05K7/14
CPC Code(s): H05K7/1488
Abstract: a datacenter including a plurality of racks. the racks associated with a motorized and/or automated system to move the racks between first and second positions. in the first position, the racks are arranged in a side-by-side fashion in one or more rows. in the second position, a rack is moved so that a lateral side of the rack is accessible. in some embodiments, the racks include a motor and gear system for interacting with tracks. in some embodiments, each of the racks includes a plurality of chassis, each chassis including a plurality of input/output (i/o) connectors to receive a connector of a cable, the plurality of i/o connectors are arranged along a lateral side of the chassis so that they are accessible when the rack is in the second position. in use, the racks may be moved between the first and second positions while the chassis remain in normal operation.
Inventor(s): Sudipto NASKAR of Portland OR US for intel corporation, Manish CHANDHOK of Beaverton OR US for intel corporation, Abhishek A. SHARMA of Portland OR US for intel corporation, Roman CAUDILLO of Portland OR US for intel corporation, Scott B. CLENDENNING of Portland OR US for intel corporation, Cheyun LIN of Portland OR US for intel corporation
IPC Code(s): H10B12/00
CPC Code(s): H10D1/042
Abstract: embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. the three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. a capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. other embodiments may be described and/or claimed.
Inventor(s): Brandon Christian Marin of Gilbert AZ US for intel corporation, Whitney Bryks of Tempe AZ US for intel corporation, Gang Duan of Chandler AZ US for intel corporation, Jeremy Ecton of Gilbert AZ US for intel corporation, Jason Gamba of Gilbert AZ US for intel corporation, Haifa Hariri of Phoenix AZ US for intel corporation, Sashi Shekhar Kandanur of Phoenix AZ US for intel corporation, Joseph Peoples of Gilbert AZ US for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ US for intel corporation, Mohammad Mamunur Rahman of Gilbert AZ US for intel corporation, Bohan Shan of Chandler AZ US for intel corporation, Joshua James Stacey of Chandler AZ US for intel corporation, Hiroki Tanaka of Gilbert AZ US for intel corporation, Jacob Ryan Vehonsky of Chandler AZ US for intel corporation
IPC Code(s): H10D1/20, H01L23/15, H01L23/538, H01L25/18
CPC Code(s): H10D1/20
Abstract: package substrates with components included in cavities of glass cores are disclosed. an example apparatus includes: a glass core having a first opening and a second opening spaced apart from the first opening, the second opening having a greater width than the first opening. the example apparatus further includes a conductive material adjacent a first wall of the first opening; and a dielectric material adjacent a second wall of the second opening.
Inventor(s): Sanjay Rangan of Albuquerque NM US for intel corporation, Adam Brand of Mountain View CA US for intel corporation, Chen-Guan Lee of Portland OR US for intel corporation, Rahul Ramaswamy of Portland OR US for intel corporation, Hsu-Yu Chang of Hillsboro OR US for intel corporation, Adithya Shankar of Hillsboro OR US for intel corporation, Marko Radosavljevic of Portland OR US for intel corporation
IPC Code(s): H01L29/08, H01L27/092, H01L29/06, H01L29/417, H01L29/423, H01L29/775
CPC Code(s): H10D62/151
Abstract: described herein are gate-all-around (gaa) transistors with extended drains, where the drain region extends through a well region below the gaa transistor. a high voltage can be applied to the drain, and the extended drain region provides a voltage drop. the transistor length (and, specifically length of the extended drain) can be varied based on the input voltage to the device, e.g., providing a longer drain for higher input voltages. the extended drain transistors can be implemented in devices that include cfets, either by implementing the extended drain transistor across both cfet layers, or by providing a sub-fin pedestal with the well regions in the lower layer.
Inventor(s): Leonard P. GULER of Hillsboro OR US for intel corporation, Biswajeet GUHA of Hillsboro OR US for intel corporation, Tahir GHANI of Portland OR US for intel corporation, Swaminathan SIVAKUMAR of Beaverton OR US for intel corporation
IPC Code(s): H10D30/00, H10D62/10, H10D84/01, H10D84/83
CPC Code(s): H10D64/017
Abstract: gate-all-around integrated circuit structures having oxide sub-fins, and methods of fabricating gate-all-around integrated circuit structures having oxide sub-fins, are described. for example, an integrated circuit structure includes an oxide sub-fin structure having a top and sidewalls. an oxidation catalyst layer is on the top and sidewalls of the oxide sub-fin structure. a vertical arrangement of nanowires is above the oxide sub-fin structure. a gate stack is surrounding the vertical arrangement of nanowires and on at least the portion of the oxidation catalyst layer on the top of the oxide sub-fin structure.
- Intel Corporation
- G02B6/132
- G02B6/12
- G02B6/136
- CPC G02B6/132
- Intel corporation
- G06F1/26
- G06F12/0875
- CPC G06F1/3209
- G06F1/3231
- G06F1/3234
- G06N20/00
- G06V40/10
- G10L15/08
- G10L15/18
- G10L15/22
- G10L15/30
- H04N23/65
- H04W52/02
- CPC G06F1/3231
- G06F9/30
- G06F9/38
- CPC G06F9/30025
- G06F7/78
- CPC G06F9/30036
- G06F9/54
- G06F9/455
- G06F9/48
- G06F15/17
- CPC G06F9/5077
- G06F11/10
- H04L9/32
- H04L69/22
- CPC G06F11/1004
- G06F12/02
- CPC G06F12/023
- G06F12/0893
- CPC G06F12/0811
- G06F13/16
- CPC G06F13/1668
- G06F15/78
- G06F7/544
- G06F7/575
- G06F7/58
- G06F9/50
- G06F12/06
- G06F12/0802
- G06F12/0804
- G06F12/0811
- G06F12/0862
- G06F12/0866
- G06F12/0871
- G06F12/0882
- G06F12/0891
- G06F12/0895
- G06F12/0897
- G06F12/1009
- G06F12/128
- G06F15/80
- G06F17/16
- G06F17/18
- G06N3/08
- G06T1/20
- G06T1/60
- G06T15/06
- H03M7/46
- CPC G06F15/7839
- CPC G06F15/8046
- G06F21/79
- G06F12/14
- G06F13/28
- G06F21/60
- G06F21/62
- G06F21/85
- CPC G06F21/602
- G06N3/0475
- CPC G06N3/0475
- G06N3/063
- G06F18/21
- G06F18/214
- G06N3/047
- G06N3/084
- CPC G06N3/063
- G06N5/04
- G06N3/02
- CPC G06N5/04
- CPC G06T1/20
- G06F1/3203
- G06F11/34
- CPC G06T15/005
- H01L23/00
- H01L23/31
- H05K1/18
- CPC H01L23/49811
- H01L23/498
- H01L23/538
- H01L25/065
- CPC H01L23/49822
- H01L25/11
- CPC H01L24/29
- H01R13/6471
- H01R12/70
- H01R12/71
- H01R12/75
- H01R13/04
- CPC H01R13/6471
- H04L41/0631
- H04L41/069
- H04L41/16
- H04W24/02
- CPC H04L41/0631
- H04L47/24
- H04L47/12
- H04L47/26
- CPC H04L47/24
- H04L49/253
- H04L49/112
- CPC H04L49/254
- H04W12/041
- H04W12/033
- H04W12/0433
- CPC H04W12/0433
- H04L5/00
- CPC H04W24/04
- H04W72/1268
- H04W76/38
- CPC H04W72/1268
- H05K7/14
- CPC H05K7/1488
- H10B12/00
- CPC H10D1/042
- H10D1/20
- H01L23/15
- H01L25/18
- CPC H10D1/20
- H01L29/08
- H01L27/092
- H01L29/06
- H01L29/417
- H01L29/423
- H01L29/775
- CPC H10D62/151
- H10D30/00
- H10D62/10
- H10D84/01
- H10D84/83
- CPC H10D64/017