Category:Subramaniam Maiyuran of Gold River CA US
Subramaniam Maiyuran
Subramaniam Maiyuran from Gold River CA US has applied for patents in technology areas such as G06F15/78, G06F7/544, G06F7/575 with intel corporation.
Patents
Pages in category "Subramaniam Maiyuran of Gold River CA US"
The following 26 pages are in this category, out of 26 total.
1
- 18905667. SYSTEMS AND METHODS FOR CACHE OPTIMIZATION (Intel Corporation)
- 18906428. CACHE STRUCTURE AND UTILIZATION (Intel Corporation)
- 18906859. SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE (Intel Corporation)
- 18907092. SYSTEMS AND METHODS FOR ERROR DETECTION AND CONTROL FOR EMBEDDED MEMORY AND COMPUTE ELEMENTS (Intel Corporation)
- 18915492. MULTI-TILE MEMORY MANAGEMENT (Intel Corporation)
- 18931412. SYSTOLIC ARRAY OF ARBITRARY PHYSICAL AND LOGICAL DEPTH (Intel Corporation)
- 18948174. SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION (Intel Corporation)
- 18955259. DATA LOCALITY ENHANCEMENT FOR GRAPHICS PROCESSING UNITS (Intel Corporation)
- 18967172. ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY (Intel Corporation)
2
I
- Intel corporation (20240256274). SUPPORTING 8-BIT FLOATING POINT FORMAT OPERANDS IN A COMPUTING ARCHITECTURE
- Intel corporation (20240256456). DATA PREFETCHING FOR GRAPHICS DATA PROCESSING
- Intel corporation (20240256483). GRAPHICS PROCESSOR DATA ACCESS AND SHARING
- Intel corporation (20240257294). COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS
- Intel corporation (20250004981). MULTI-TILE MEMORY MANAGEMENT
- Intel corporation (20250103343). DATA LOCALITY ENHANCEMENT FOR GRAPHICS PROCESSING UNITS
- Intel corporation (20250103430). SYSTEMS AND METHODS FOR ERROR DETECTION AND CONTROL FOR EMBEDDED MEMORY AND COMPUTE ELEMENTS
- Intel corporation (20250103511). SYSTEMS AND METHODS FOR CACHE OPTIMIZATION
- Intel corporation (20250103546). CACHE STRUCTURE AND UTILIZATION
- Intel corporation (20250103547). SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE
- Intel corporation (20250103548). SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION
- Intel corporation (20250104180). ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY
- Intel corporation (20250117356). MULTI-TILE MEMORY MANAGEMENT
- Intel corporation (20250117360). SYSTOLIC ARRAY OF ARBITRARY PHYSICAL AND LOGICAL DEPTH
Categories:
- Inventors
- Intel corporation
- G06F15/78
- G06F7/544
- G06F7/575
- G06F7/58
- G06F9/30
- G06F9/38
- G06F9/50
- G06F12/02
- G06F12/06
- G06F12/0802
- G06F12/0804
- G06F12/0811
- G06F12/0862
- G06F12/0866
- G06F12/0871
- G06F12/0875
- G06F12/0882
- G06F12/0891
- G06F12/0893
- G06F12/0895
- G06F12/0897
- G06F12/1009
- G06F12/128
- G06F15/80
- G06F17/16
- G06F17/18
- G06N3/08
- G06T1/20
- G06T1/60
- G06T15/06
- H03M7/46